MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 350

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Multi-port DRAM Controller Priority Manager
All counters in
registers associated with every counter. The first register is the counter. It counts the events mentioned in
the table. When the trigger condition occurs, the time event counter reaches zero, and the counter register
is transferred to the buffer register, the counter register is then cleared. When accessing the register, the
buffer register value is always returned.
The priority code added may or may not be the same as the priority code the request used on the DRAM
controller. The codes are equal if the LUT SEL bitfield for the channel is the same in the
PRIOMAN_CONFIG and PERMON_CONFIG registers. If the LUT SEL bitfields differ, the bitfield in
PRIOMAN_CONFIG is used to calculate the channel priority code on the DRAM, and the bitfield in
PERMON_CONFIG is used to calculate the priority code added to this register.
12-18
SUMMED PRIORITY COUNTER 0–4 Every time a request is granted by the multi-port DRAM controller for channel 0 – 4, a
CUMULATIVE WAIT COUNTER 0–4 Every time there is a request pending to the multi-port DRAM controller for channel
PERFORMANCE MONITOR 1–2
PERFORMANCE MONITOR 1–2
GRANTED ACK COUNTER 0–4
WRITE COUNTER
READ COUNTER
Field
Trigger Condition condition
Table 12-17
are double-buffered and
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 12-17. Monitor Counter Descriptions
Event
Every time the Processor performs a read access with an address that hits in the
address window for counter 1 or 2, the respective counter is incremented. An address
hits in the address window for performance monitor read counter 1 if the address is
higher or equal than the performance monitor 1 address low, and lower than the
performance monitor 1 address high. Similar for the second counter.
Every time the Processor performs a write access with an address that hits in the
address window for counter 1 or 2, the respective counter is incremented. An address
hits in the address window for performance monitor write counter 1 if the address is
higher or equal than the performance monitor 1 address low, and lower than the
performance monitor 1 address high. Similar for the second counter.
Every time the Multi-port DRAM controller grants a request for channel 0 – 4, the
respective counter is incremented.
0 – 4 and its not granted in the current cycle, the respective counter is incremented.
priority code is added to the respective counter. See text for details.
Figure 12-17. Monitor Counters
Counter register
+1
R
Figure 12-17
Buffer register
En
Description
gives details. There are always two
Readable value
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