MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 434

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

General Purpose I/O (GPIO)
16.3.1.6
The GPIO interrupt control register 1 (GPIO_GPICR1) and GPIO interrupt control register 2
(GPIO_GPICR2) shown in
to set their associated bit in the GPIO interrupt event register and, if enabled, causes an interrupt to be
asserted to the CPU.
NOTEThe D[0:31] bit fields of the GPIO interrupt control registers specify which type of event causes an
16-6
Address: Base + 0x10
Reset
Reset
interrupt for GPIO [0:31]. The interrupt function for each GPIO pin is individually programmable.
D[0:31]
Field
W
W
R
R
D16
D0
16
0
0
0
GPIO Interrupt Control Register 1 and 2 (GPIO_GPICR1 and
GPIO_GPICR2)
Bits D0–D31 of the GPIO_GPIMR register in GPIO1 mask interrupts from
the GPIO 00–31 pins. Bits D0–D31 of the GPIO_GPIMR register in GPIO2
mask interrupts from the GPIO 32–63 pins.
The D[0:31] bit fields of the GPIO_GPICR1 and GPIO_GPICR2 registers
in GPIO1 specify the interrupt event type for GPIO pins 00–31. The D[0:31]
bit fields of the GPIO_GPICR1 and GPIO_GPICR2 registers in GPIO2
specify the interrupt event type for GPIO pins 32–63.
Interrupt mask. Indicates whether an interrupt event is masked or non-masked.
0 The input interrupt pin is masked (disabled).
1 The input interrupt pin is non-masked (enabled).
D17
D1
17
0
0
1
D18
D2
18
0
0
2
Figure 16-6. GPIO Interrupt Mask Register (GPIO_GPIMR)
Figure 16-7
D19
D3
19
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 16-6. GPIO_GPIMR field descriptions
D20
D4
20
4
0
0
D21
determines which type of event causes each individual GPIO pin
D5
21
0
0
5
D22
D6
22
0
0
6
NOTE
D23
D7
23
0
0
7
Description
D24
D8
24
8
0
0
D25
D9
25
9
0
0
D10
D26
10
26
0
0
D11
D27
11
27
0
0
D12
D28
12
28
0
0
Freescale Semiconductor
Access: User read/write
D13
D29
13
29
0
0
D14
D30
14
30
0
0
D15
D31
15
31
0
0