MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 896

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32.5.5
This data structure is used only with a queue head. This data structure is for one or more USB transactions.
This data structure transfers as many as 20480 (5 × 4096) bytes. The structure contains two structure
pointers used for queue advancement, a doubleword of transfer state, and a five-element array of data
buffer pointers. This structure is 32 bytes (or one 32-byte cache line). This data structure must be
physically contiguous.
The buffer associated with this transfer must be virtually contiguous. The buffer may start on any byte
boundary. A separate buffer pointer list element must be used for each physical page in the buffer,
regardless of whether the buffer is physically contiguous.
Host controller updates (host controller writes) to stand-alone qTDs only occur during transfer retirement.
References in the following bit field definitions of updates to the qTD are to the qTD portion of a queue
head.
1
Queue element transfer descriptors must be aligned on 32-byte boundaries.
32.5.5.1
The first doubleword of an element transfer descriptor is a pointer to another transfer element descriptor.
32-68
dt
31
Host controller read/write; all others read-only.
1
Next qTD
Pointer
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
31:5
Bit
4:1
0
T
Queue Element Transfer Descriptor (qTD)
Next qTD Pointer
This field contains the physical memory address of the next qTD to be processed. The field corresponds to
memory address signals[31:5], respectively.
Reserved. These bits are reserved and their value has no effect on operation.
Terminate. This bit indicates to the Host Controller that there are no more valid entries in the queue.
0 Pointer is valid (points to a valid Transfer Element Descriptor).
1 Pointer is invalid.
Total Bytes to Transfer
Table 32-57. qTD Next Element Transfer Pointer (doubleword 0)
Buffer Pointer (Page 0)
Buffer Pointer (Page 1)
Buffer Pointer (Page 2)
Buffer Pointer (Page 3)
Buffer Pointer (Page 4)
Figure 32-48. Queue Element Transfer Descriptor (qTD)
MPC5125 Microcontroller Reference Manual, Rev. 2
Alternate Next qTD Pointer
Next qTD Pointer
1
IO
15
C
14 13 12 11 10
C_Page
Description
1
Cerr
1
Code
9
PID
8
0000_0000_0000
0000_0000_0000
0000_0000_0000
0000_0000_0000
Current Offset
7
6
5
Status
Freescale Semiconductor
4
1
0000
0000
3
1
2
1
T 0x00
T 0x04
0
0x0C
0x1C
0x08
0x10
0x14
0x18
offset