MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 898

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32-70
PID Code
11:10
Cerr
9:8
Bit
Error Counter. This field is a 2-bit down counter that keeps track of the number of consecutive errors detected
while executing this qTD. If this field is programmed with a non-zero value during set-up, the host controller
decrements the count and writes it back to the qTD if the transaction fails. If the counter counts from one to
zero, the host controller marks the qTD inactive, sets the halted bit to a one, and error status bit for the error
that caused Cerr to decrement to zero. An interrupt is generated if the USB error interrupt enable bit in the
USB_USBINTR register is set. If the host controller driver (HCD) software programs this field to zero during
set-up, the host controller does not count errors for this qTD and there is no limit on the retries of this qTD.
Write-backs of intermediate execution state are to the queue head overlay area, not the qTD.
Transaction Error Yes
Data Buffer Error
Stalled
Babble Detected
No Error
This field is an encoding of the token, which should be used for transactions associated with this transfer
descriptor. Encodings are:
00 OUT Token generates token (E1H)
01 IN Token generates token (69H)
10 SETUP Token generates token (2DH) (undefined if endpoint is an Interrupt transfer type, for example.
11 Reserved
µFrame S-mask field in the queue head is non-zero.)
Error
Table 32-59. qTD Token (doubleword 2) (continued)
MPC5125 Microcontroller Reference Manual, Rev. 2
No. Data buffer errors are host problems. They don't count against the device's retries.
Software must not program Cerr to a value of zero when the EPS field is programmed with
a value indicating a full- or low-speed device. This combination could result in undefined
behavior.
No.
decremented
No.
decremented
No.
schedule (and PIDCode indicates an IN or OUT), a bus transaction completes, and the host
controller does not detect a transaction error, the host controller should reset Cerr to extend
the total number of errors for this transaction. For example, Cerr should be reset with
maximum value (0b11) on each successful completion of a transaction. The host controller
must never reset this field if the value at the start of the transaction is 0b00.
Detection of babble or stall automatically halts the queue head. Count is not
Detection of babble or stall automatically halts the queue head. Count is not
If the EPS field indicates a HS device or the queue head is in the asynchronous
Description
Decrement Counter
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