MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 686

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Programmable Serial Controller (PSC)
25.4.1.2
The second register to control the configuration.
25-8
10
11
Address: Base + 0x04
Address: Base + 0x04
TxRTS
TxCTS
Reset
Reset
Field
CM
W
W
R
R
Mode Register 2 (MR2)
Channel mode. Selects a channel mode. CM is used in UART and codec modes.
00 Normal.
01 Automatic echo.
10 Local loop-back.
11 Remote loop-back.
UART. Transmitter ready-to-send. Controls negation of RTS to automatically terminate a message
transmission. Attempting to program a receiver and transmitter in the same channel for RTS control is not
permitted and disables RTS control for both. TxRTS is not used in codec mode.
0 The transmitter has no effect on RTS .
1 Setting this bit automatically clears RTS line one bit-time after any characters in the transmitter shift
Other Modes. Reserved.
UART. Transmitter clear-to-send. If TxCTS and TxRTS are enabled, TxCTS controls the operation of the
transmitter. TxCTS is not used in Codec mode.
0 CTS has no effect on the transmitter.
1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a
If CTS is asserted, the character is sent.
If it is negated, the channel TxD remains in a high state and transmission is delayed until CTS is asserted.
Changes in CTS as a character is being sent do not affect its transmission.
Other Modes. Reserved.
0
0
0
0
Multidrop mode
registers are completely sent, including the programmed number of stop bits.
character.
No parity
CM
CM
Figure 25-7. Mode Register 2 for Other Modes (MR2)
Figure 25-6. Mode Register 2 for UART Mode (MR2)
1
0
1
0
Table 25-5. Parity Mode/Parity Type Definitions
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 25-6. MR2 field descriptions
TxRTS
0
0
0
2
2
TxCTS
0
0
0
3
3
Data character
Description
0
0
4
4
n/a
RX -TX Channels
0
0
5
5
SB
Address character
Freescale Semiconductor
Access: User read/write
Access: User read/write
0
0
6
6
0
0
7
7