MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 151

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Write: write only once.
Freescale Semiconductor
Address: Base + 0x08
RXPOL
BO[4:0[
Reset
Field
W
R
BARD Offset Bits BO[4:0]
Table 6-10. BARD Values vs. Transceiver Delay and Transmitter Timing Adjustment
Receive Pin Polarity
The Receive pin Polarity bit is used to select the polarity of incoming signal on the receive pin. Some external
analog transceiver inverts the receive signal from the J1850 bus before feeding back to the digital receive pin.
0 Select inverted polarity, where external transceiver inverts the receive signal.
1 Select normal/true polarity; true non-inverted signal from J1850 bus, i.e., the external transceiver does not
BDLC Analog Roundtrip Delay Offset Field
Adjust the transmitted symbol timings to account for the differing round-trip delays found in different SAE
J1850 analog transceivers.The allowable delay range is from 0 ms to 31 ms, with a nominal target of 16 ms
(reset value). Refer to
the resultant transmitter timing adjustment (in MUX interface clock periods (t
transceiver device specification for the expected round-trip delay through both the transmitter and the receiver.
The sum of these two delays makes up the total round-trip delay value.
Note: For Digital Loopback test, the Analog Round-trip Delay Offset Field should be set to 0 µs.
0
0
0
Figure 6-7. BDLC Analog Round Trip Delay Register (BDLC_DLCBARD)
invert the receive signal.
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
RXPOL
1
0
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 6-9. BDLC_DLCBARD field descriptions
Table 6-10
Corresponding Expected
Transceiver’s delays (µs)
0
0
2
for the BO[4:0] values corresponding to the expected transceiver delays and
10
11
12
13
14
0
1
2
3
4
5
6
7
8
9
BO4
0
3
Description
BO3
0
4
Transmitter Symbol Timing
Adjustment (t
BO2
0
5
bdlc
10
11
12
13
14
0
1
2
3
4
5
6
7
8
9
Byte Data Link Controller (BDLC)
)). Refer to the analog
bdlc
Access: User read/write
BO1
1
0
6
)
BO0
0
7
6-15