MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 173

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.4.4.1.3
The digital loopback multiplexer connects the input of the receive digital filter (See
the transmit signal out to the pad (J1850_TX) or the receive signal from the pad (J1850_RX), depending
on the DLOOP bit in BDLC Control Register 2 register.
6.4.4.1.4
All of the functions associated with performing the protocol are executed or controlled by the State
Machine. The State Machine is responsible for framing, collision detection, arbitration, CRC
generation/checking, and error detection. The following sections describe the BDLC module’s actions in
a variety of situations.
6.4.4.1.5
The BDLC module can exist on the same J1850 bus as modules that use a special 4X (41.6 kbit/s) mode
of J1850 VPW operation. The BDLC module can transmit and receive messages in 4X mode, if the 4XE
bit is set in BDLC Control Register 2. If the 4XE bit is not set in the BDLC Control Register 2, any 4X
message on the J1850 bus is treated as noise by the BDLC module and is ignored. Likewise, 4X messages
transmitted on the SAE J1850 bus when the BDLC module is in normal mode is interpreted as noise on
the network by the BDLC module.
6.4.4.1.6
Although not a part of the SAE J1850 protocol, the BDLC module allows for a special block mode of
operation for the receiver. As far as the BDLC module is concerned, a block mode message is simply a
long J1850 frame that contains an indefinite number of data bytes. All of the other features of the frame
remain the same, including the SOF, CRC, and EOD symbols.
Another node wishing to send a block mode transmission must first inform all other nodes on the network
that this is about to happen. This is usually accomplished by sending a special predefined message.
6.4.4.1.7
A Block mode message is transmitted inherently by simply loading the bytes one by one into the BDLC
Data Register register until the message is complete. The programmer should wait until the TDRE flag is
set prior to writing a new byte of data into the BDLC Data Register register. The BDLC module does not
contain any predefined maximum J1850 message length requirement.
6.4.5
The design of the BDLC module enables the separate management of message reception and message
transmission. All received messages can be managed almost identically, regardless of their origin.
This chapter only describes the steps necessary for transmitting a message and does not address the
resulting reception of that message by the BDLC module. Message reception is described in
“Receiving A Message.”
SAE J1850 bus.
Freescale Semiconductor
Transmitting a Message
Digital Loopback Multiplexer
State Machine
4X Mode
Receiving a Message in Block Mode
Transmitting a Message in Block Mode
Later sections deal with transmitting and receiving In-Frame Responses on the
MPC5125 Microcontroller Reference Manual, Rev. 2
Byte Data Link Controller (BDLC)
Figure
6-19) to either
Section 6.4.6,
6-37