MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 114

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Clocks and Low-Power Modes
5.3.1.5
The System Clock Frequency Register 2 (SCFR2) shown in
values written to this register are visible after some update cycles. Changing this register value unlocks the
Power Architecture PLL, because the source clock of the Power Architecture PLL is derived from the
SYS_CLK.
1
5-14
Address: Base + 0x10
The reset value is defined by the latched reset configuration word (RST_CONF). See
Reset
Reset
DIU_DIV
Field
W
W
R
R
16
0
0
0
System Clock Frequency Register 2 (SCFR2)
Display Interface Unit (DIU) clock divide ratio
17
0
0
1
SYS_DIV
1
18
0
0
2
0b0000_1000
0b0000_1100
0b0000_1101
0b0000_1110
0b0000_1111
0b0001_0000
0b0001_0001
0b1111_1011
0b1111_1100
0b1111_1101
0b1111_1110
0b1111_1111
This option should not be used.
Figure 5-10. System Clock Frequency Register (SCFR2)
SDHC2_DIV
DIV
—
19
0
Table 5-9. SCFR1 field descriptions (continued)
3
MPC5125 Microcontroller Reference Manual, Rev. 2
1
—
20
4
1
1
DIV value (decimal)
—
21
0
5
12 (default)
1
251
252
253
254
255
13
14
15
16
17
8
n
22
0
0
0
6
. . .
. . .
23
0
0
0
7
Description
CSB_CLK:DIU_CLK
Figure 5-10
24
8
0
0
0
62.75
63.25
63.75
3.25
3.75
4.25
63.5
25
9
0
0
0
3.5
n/4
63
2
3
4
1
programs the SYS_DIV ratio. The
10
26
0
0
0
Table
SDHC1_DIV
11
27
0
0
0
4-2.
12
28
0
0
1
Freescale Semiconductor
Access: User read/write
13
29
0
0
0
14
30
0
0
0
15
31
0
0
0