MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 892

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32.5.4
All full-speed isochronous transfers through the internal transaction translator are managed using the siTD
data structure. This data structure satisfies the operational requirements for managing the split transaction
protocol.
32.5.4.1
Doubleword0 of an siTD is a pointer to the next schedule data structure.
32-64
1
I/O
Buffer Pointer
IO
31
C
Host controller read/write; all others read-only.
Next Link
Pointer
31:12
Field
P
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
11:2
31:5
Typ
Bit
4:3
2:1
1
0
T
Port Number
0000
Split Transaction Isochronous Transfer Descriptor (siTD)
Next Link Pointer
This is a 4 K aligned pointer to physical memory. Corresponds to memory address bits [31:12].
Reserved. These bits reserved for future use and should be cleared.
This field contains the address of the next data object to be processed in the periodic list and corresponds to
memory address signals [31:5], respectively.
Reserved. These bits must be written as zeros.
This field indicates to the host controller whether the item referenced is an iTD/siTD or a QH. This allows the
host controller to perform the proper type of processing on the item after it is fetched. Value encodings are:
00 iTD (isochronous transfer descriptor)
01 QH (queue head)
10 siTD (split transaction isochronous transfer descriptor
11 FSTN (frame span traversal node)
Terminate.
0 Link Pointer is valid.
1 Link Pointer field is not valid.
0000_0000_0000_00000
Figure 32-47. Split-Transaction Isochronous Transaction Descriptor (siTD)
Buffer Pointer (Page 0)
Buffer Pointer (Page 1)
Total Bytes to Transfer
0
MPC5125 Microcontroller Reference Manual, Rev. 2
Hub Address
Table 32-49. Buffer Pointer Page 3-6
Next Link Pointer
Back Pointer
Table 32-50. Next Link Pointer
1
15
µFrame C-prog-mask
0000
Description
Description
14 13 12 11 10
µFrame C-mask
EndPt
000_0000
9
1
8
Current Offset
0
7
6
µFrame S-mask
Device Address
5
Status
Freescale Semiconductor
4
TP
00
1
1
0000
3
1
2
T-count
Typ
1
T 0x00
T 0x18
0
1
0x0C
0x04
0x08
0x10
0x14
offset