MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 601

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

22.3.2.14 MSCAN Receive Error Counter Register (CANRXERR)
This register reflects the status of the MSCAN receive error counter.
Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and
INITAK = 1).
Write: Unimplemented
22.3.2.15 MSCAN Transmit Error Counter Register (CANTXERR)
This register reflects the status of the MSCAN transmit error counter.
Freescale Semiconductor
BOFFHOLD
RXERR[7:0]
Address: Base + 0x19
Address: Base + 0x1C
Reset
Reset
Field
Field
W
W
R
R
RXERR7
Reading this register when in any other mode other than sleep or
initialization mode may return an incorrect value.
Bus-off State Hold Until User Request.
If BORM is set in MSCAN Control Register 1 (see
this bit indicates whether the module has entered the bus-off state. Clearing this bit requests the recovery from
bus-off. Refer to
0 Module is not bus-off or recovery has been requested by user in bus-off state.
1 Module is bus-off and holds this state until user request.
This register reflects the status of the MSCAN receive error counter.
Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and
INITAK = 1)
0
0
0
0
0
Figure 22-16. MSCAN Receive Error Counter Register (CANRXERR)
RXERR6
1
0
0
1
0
Figure 22-15. MSCAN MISC Register (CANMISC)
Section 22.4.15, “Bus-Off Recovery,”
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 22-17. CANRXERR field descriptions
Table 22-16. CANMISC field descriptions
RXERR5
0
0
0
2
2
RXERR4
NOTE
0
0
0
3
3
Description
Description
Section 22.3.2.2, “MSCAN Control 1 Register
RXERR3
for details.
0
0
0
4
4
RXERR2
0
0
0
5
5
RXERR1
Access: User read/write
Access: User read-only
0
0
0
6
6
(CANCTL1)”),
BOFFHOLD
RXERR0
w1c
0
0
7
7
MSCAN
22-23