MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 278

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Display Interface Unit (DIU)
10.3.3.14 Horizontal Sync Pulse Parameters Register (HSYN_PARA)
The Horizontal Sync Pulse Parameters Register (HSYN_PARA) sets timing parameters related to the
horizontal synchronization signal generation. See
signal meaning.
10.3.3.15 Vertical Sync Pulse Parameters Register (VSYN_PARA)
The Vertical Sync Pulse Parameters Register (VSYN_PARA) sets timing parameters related to the vertical
synchronization signal generation. See
meaning.
10-16
Address: Base + 0x34
Address: Base + 0x38
Reset
Reset
Reset
Reset
PW_H
BP_H
FP_H
Field
W
W
W
W
R
R
R
R
16
16
0
0
0
0
0
0
HSYNC back-porch pulse width (in pixel clock cycles). It can be 0.
HSYNC active pulse width (in pixel clock cycles). It must be greater than or equal to 1.
HSYNC front-porch pulse width (in pixel clock cycles). It can be 0.
17
17
0
0
0
0
1
1
Figure 10-14. Horizontal Sync Pulse Parameters Register (HSYN_PARA)
Figure 10-15. Vertical Sync Pulse Parameters Register (VSYN_PARA)
PW_H
PW_V
18
18
0
0
0
0
2
2
19
19
0
0
0
0
3
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 10-17. HSYN_PARA field descriptions
20
20
4
0
0
4
0
0
BP_H
BP_V
Figure
21
21
0
0
0
0
0
0
5
5
10-50, the display timing diagram, for detailed signal
22
22
0
0
0
0
6
6
Figure
23
23
0
0
0
0
7
7
Description
10-49, the display timing diagrams, for detailed
24
24
8
0
0
8
0
0
25
25
9
0
0
9
0
0
10
26
10
26
0
0
0
0
0
0
FP_H
FP_V
11
27
11
27
0
0
0
0
12
28
12
28
0
0
0
0
Freescale Semiconductor
Access: User read/write
Access: User read/write
PW_H
PW_V
13
29
13
29
0
0
0
0
14
30
14
30
0
0
0
0
15
31
15
31
0
0
0
0