MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 667

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
2
24.2.2.2
Freescale Semiconductor
Address: Base + 0x04
PRE
DIV
Power Architecture core initiates nap mode entry by setting the e300 NAP bit in the HID register while the POW bit in MSR
register is set.
Power Architecture core initiates sleep mode entry by setting the e300 SLEEP bit in the HID register while the POW bit in MSR
register is set.
0
1
1
Reset
Reset
W
W
R
R
CCM
1
0
0
All other values
16
0
0
0
0
0
PMC Event Register (PMC_PMCER)
DSM
0
0
0
17
0
0
0
0
1
DDR
OFF
0
0
1
18
0
0
0
0
2
Table 24-2. PMC_PMCCR field descriptions (continued)
CORE
OFF
19
Figure 24-2. PMC Event Register (PMC_PMCER)
0
0
0
0
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
When Power Architecture core hits breakpoint: undefined, reserved.
When Power Architecture core initiates nap mode entry: undefined, reserved.
When Power Architecture core initiates sleep mode entry: enter core PLL change mode.
PMC_PMCCR is cleared after return to full power mode
When Power Architecture core hits breakpoint: undefined, reserved.
When Power Architecture core initiates nap mode entry: undefined, reserved.
When Power Architecture core initiates sleep mode entry: enter Pre divider copy mode.
PMC_PMCCR is cleared after return to full power mode.
When Power Architecture core hits breakpoint: undefined, reserved.
When Power Architecture core initiates nap mode entry: undefined, reserved.
When Power Architecture core initiates sleep mode entry: put DRAM in self-refresh
mode and enter Pre-divider copy mode.
PMC_PMCCR is cleared after return to full power mode.
Undefined, reserved
20
4
0
0
0
0
21
0
0
0
0
5
22
0
0
0
0
6
23
0
0
0
0
7
24
8
0
0
0
0
Description
25
9
0
0
0
0
10
26
0
0
0
0
Power Management Control Module (PMC)
11
27
0
0
0
0
12
28
0
0
0
0
Access: User read/write
WDTO INT2
w1c
13
29
0
0
0
w1c
14
30
0
0
0
INT1
w1c
15
31
24-3
0
0
0