MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 852

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
The interrupts to software are enabled with this register. An interrupt is generated when a bit is set and the
corresponding interrupt is active. The USB_USBSTS register continues to show interrupt sources even if
the USB_USBINTR register disables them, allowing polling of interrupt events by the software.
32-24
Address: Base + 0x148
(USBERRINT)
Reset
Reset
(USBINT)
Field
Field
UPIA
UAIE
TIE1
TIE0
UEI
W
W
UI
R
R
16
0
0
0
0
0
USB Error Interrupt (USBERRINT). When completion of a USB transaction results in an error condition, this
bit is set by the controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt
occurred also had its interrupt on complete (IOC) bit set. See
on device error matrix. All others are ignored.
0 No error.
1 Error detected.
USB Interrupt (USBINT). This bit is set by the controller when the cause of an interrupt is a completion of a
USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also
set by the controller when a short packet is detected. A short packet is when the actual number of bytes
received was less than the expected number of bytes.
General Purpose Timer Interrupt Enable 1
When this bit is a 1 and the GPTINT1 bit in the USB_USBSTS register is also a 1, the controller issues an
interrupt. The interrupt is acknowledged by software clearing the GPTINT1 bit.
General Purpose Timer Interrupt Enable 0
When this bit is a 1 and the GPTINT0 bit in the USB_USBSTS register is also a 1, the controller issues an
interrupt. The interrupt is acknowledged by software clearing the GPTINT0 bit.
USB Host Periodic Interrupt Enable
When this bit is a 1 and the USBHSTPERINT bit in the USB_USBSTS register is also a 1, the host controller
issues an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the
USBHSTPERINT bit.
USB Host Async. Interrupt Enable
When this bit is a 1 and the USBHSTASYNCINT bit in the USB_USBSTS register is also a 1, the host
controller issues an interrupt at the next interrupt threshold. The interrupt is acknowledged by software
clearing the USBHSTASYNCINT bit.
17
0
0
0
0
1
Figure 32-18. USB Interrupt Enable Register (USB_USBINTR)
18
0
0
0
0
2
Table 32-17. USB_USBSTS field descriptions (continued)
19
0
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 32-18. USB_USBINTR field descriptions
20
4
0
0
0
0
ULPI
21
E
0
0
0
5
TIE1
22
0
0
0
6
TIE0
SLE
23
0
0
7
Description
Description
SRE
24
8
0
0
0
URE
25
9
0
0
0
Table 32-97
AAE
10
26
0
0
0
in this chapter for more information
SEE
11
27
0
0
0
UPIA UAIE
FRE
12
28
0
0
Freescale Semiconductor
Access: User read/write
PCE
13
29
0
0
UEE
14
30
0
0
0
NAKE
UE
15
31
0
0