MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 712

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Programmable Serial Controller (PSC)
For example, to generate a 9600 baud rate based on an internal 66 MHz IP bus frequency and a sample
rate of 16, the register values can be calculated as follows:
Therefore,
25.5.1.3
After a hardware reset, all PSCs are in UART mode. The PSC command register (CR) enables the
transmitter. The transmitter converts parallel data from the CPU to a serial bit-stream on TxD. It
automatically sends a start bit followed by:
The LSB is sent first. Data is shifted from the Tx output on the falling edge of the clock source.
After the stop bits are sent, if no new character is in the Tx holding register, the TxD output remains high
(mark condition) and the Tx empty bit, SR[TxEMP], is set. Transmission resumes and TxEMP is cleared
when the CPU loads a new character into the PSC Tx buffer (TB).
25-34
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The programmed number of data bits
An optional parity bit
The programmed number of stop bits
If the transmitter receives a disable command, it continues until any character in the Tx shift
register is completely sent.
If the transmitter is reset through a software command, operation stops immediately.
If the clear-to-send operation is enabled, CTS must be asserted for the character to be transmitted.
If CTS is negated in the middle of a transmission, the character in the shift register is sent and TxD
remains in mark state until CTS is reasserted.
CTUR
Transmitting in UART Mode
RxD
TxD
equals 0x00 and
Rx Buffer
Tx Buffer
MPC5125 Microcontroller Reference Manual, Rev. 2
Rx, sample rate 16 or 10
Tx, sample rate 16 or 10
Divider =
Figure 25-41. Clocking Source Diagram
CTLR
16 x 9600
66 MHz
equals 0xD7.
sample rate selection for RX, CSR register
sample rate selection for TX, CSR register
= 430(decimal) = 0x00D7
clock source selection, CSR register
clock source selection, CSR register
{CTUR:CTLR}
Divider
16-Bit
IPB Clock
Freescale Semiconductor
MCLK
PSC