MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 936

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
characteristic that is tunable for each endpoint, park-mode is a policy that is applied to all high-speed queue
heads in the asynchronous schedule. It is essentially the specification of an iterator for consecutive bus
transactions to the same endpoint. All of the rules for managing bus transactions and the results of those
as defined in
consecutive times the host controller is permitted to execute from the same queue head before moving to
the next queue head in the Asynchronous List. This feature should allow the host controller to attain better
bus utilization for those devices that are capable of moving data at maximum rate, while at the same time
providing a fair service to all endpoints.
A host controller exports its capability to support this feature to system software by setting the
Asynchronous Schedule Park Capability bit in the USB_HCCPARAMS register to 1. This information
keys system software that the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule
Park Mode Count fields in the USB_USBCMD register are modifiable. System software enables the
feature by writing a one to the Asynchronous Schedule Park Mode Enable bit.
When park-mode is not enabled (Asynchronous Schedule Park Mode Enable bit in the USB_USBCMD
register is 0), the host controller must not execute more than one bus transaction per high-speed queue
head, per traversal of the asynchronous schedule. When park-mode is enabled, the host controller must not
apply the feature to a queue head whose EPS field indicates a Low/Full-speed device (i.e., only one bus
transaction is allowed from each Low/Full-speed queue head per traversal of the asynchronous schedule).
Park-mode may only be applied to queue heads in the Asynchronous schedule whose EPS field indicates
that it is a high-speed device.
The host controller must apply park mode to queue heads whose EPS field indicates a high-speed endpoint.
The maximum number of consecutive bus transactions a host controller may execute on a high-speed
queue head is determined by the value in the Asynchronous Schedule Park Mode Count field in the
USB_USBCMD register. Software must not set Asynchronous Schedule Park Mode Enable bit to a one
and also set Asynchronous Schedule Park Mode Count field to a zero. The resulting behavior is not
defined. An example behavioral example describes the operational requirements for the host controller
implementing park-mode. This feature does not affect how the host controller handles the bus transaction
as defined in
transactions for the current queue head can be executed. All boundary conditions, error detection and
reporting applies as usual. This feature is similar in concept to the use of the Mult field for high-bandwidth
Interrupt for queue heads in the Periodic Schedule.
The host controller effectively loads an internal down-counter PM-Count from Asynchronous Schedule
Park Mode Count when Asynchronous Schedule Park Mode Enable bit is a one, and a high-speed queue
head is first fetched and meets all the criteria for executing a bus transaction. After the bus transaction,
PM-Count is decremented. The host controller may continue to execute bus transactions from the current
queue head until PM-Count goes to zero, an error is detected, the buffer for the current transfer is exhausted
or the endpoint responds with a flow-control or STALL handshake.
32.6.9.4
This state is entered from the Execute Transaction state when the Active bit is set to a zero. The source data
for the write-back is the transfer results area of the queue head overlay area (see
controller uses the Current qTD Pointer field as the target address for the qTD. The queue head transfer
32-108
Section 32.6.9.3, “Execute Transaction,”
Section 32.6.9.3, “Execute Transaction.”
Write Back qTD
MPC5125 Microcontroller Reference Manual, Rev. 2
apply. This feature merely specifies how many
It only affects how many consecutive bus
Figure
Freescale Semiconductor
32-49). The host