MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 344

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Multi-port DRAM Controller Priority Manager
12.3.2.8
12-12
EVENTCOUNT FREERUN
EVENTCOUNT TRIGGER Write-Only Bit. Writing to this bit causes all count registers to be transferred to the buffer registers,
Address: Base + 0x00DC
Reset
Reset
DMAREQSTOP
W
W
R
R
INTCLEAR
LUT SELn
DMAREQ
INTEN
Field
INT
INT
Figure 12-9. Performance Monitor Configuration (PERF_MONITOR_CONFIG) Register
16
0
0
0
0
Performance Monitor Configuration (PERF_MONITOR_CONFIG)
Register
LEAR
INTC
17
0
0
0
1
1
INTE
18
N
0
0
0
2
Read-Only Sticky Bit. Interrupt pending register. Set when interrupt is made pending.
Write-Only. Writing a 1 to this bit clears the INT bit.
Interrupt Enable. When this bit is 1 and the INT bit is 1, the processor gets an interrupt request.
DMA request. This read-only bit is set when event counter time reaches 0, and cleared when the
first counter register is read.
Read/Write.
0 DMA request functions as expected.
1 DMA request is cleared and cannot get set.
0 Event Counter Single-Shot. After reaching 0, the event time counter stays at 0 and is not
1 Event Counter Free Run. After reaching 0, the event time counter is reloaded from event time
and subsequent be cleared. It causes the event counter to be reloaded from the event time preset
register. No interrupt or DMA request is generated on writing this register, but both are generated
when the event time counter register reaches 0.
Selectors between primary and secondary look-up table configuration register.
These selectors determine which LUT table is used for the summed priority counters. The priorities
entered into these counters may depend on a different LUT table than the priorities sent to the
DRAM controller.
00 Select main look-up table configuration register
01 Select alternate look-up table configuration register
10 Select alternate look-up table configuration register if congested flag is set
11 Select alternate look-up table configuration register if DIU incoming priority bit 3 is high
Table 12-9. PERF_MONITOR_CONFIG field descriptions
reloaded.
preset and a new cycle starts.
DMA
REQ
19
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
STOP
DMA
REQ
20
4
1
0
0
EVEN
UNTF
RUN
TCO
REE
21
0
0
0
5
EVEN
UNTT
TCO
RIG
LUT SEL4
22
0
0
6
23
0
0
0
7
LUT SEL3
24
Description
8
0
0
0
25
9
0
0
0
LUT SEL2
10
26
0
0
0
11
27
0
0
0
LUT SEL1
12
28
0
0
0
Freescale Semiconductor
Access: User read/write
2
13
29
0
0
0
LUT SEL0
14
30
0
0
0
15
31
0
0
0