MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 312

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
2
3
DRAM Controller
11.3
11.3.1
11-4
(0xFF40_9000)
0x0064–0x0FFF Reserved
0x0044–0x005F Reserved
DRAM_BASE
Default absolute offset with IMMRBAR at default location of 0xFF40_0000. See
Map (XLBMEN + Mem Map).”
In this column, R/W = Read/Write, R = Read-only, and W = Write-only.
In this column, the symbol “U” indicates one or more bits in a byte are undefined at reset. See the associated description for
more information.
Offset from
0x000C
0x001C
0x002C
0x003C
0x0000
0x0004
0x0008
0x0010
0x0014
0x0018
0x0020
0x0024
0x0028
0x0030
0x0034
0x0038
0x0040
0x0060
Memory Map and Register Definition
Memory Map
1
DDR_SYS_CONFIG—DDR System Configuration Register
DDR_TIME_CONFIG0—DDR Time Config0 Register
DDR_TIME_CONFIG1—DDR Time Config1 Register
DDR_TIME_CONFIG2—DDR Time Config2 Register
DDR_COMMAND—DRAM Command Register
DDR_COMPACT_COMMAND—Compact Command Register
SELF_REFRESH_CMD_0—Self-Refresh Command Register 0
SELF_REFRESH_CMD_1—Self-Refresh Command Register 1
SELF_REFRESH_CMD_2—Self-Refresh Command Register 2
SELF_REFRESH_CMD_3—Self-Refresh Command Register 3
SELF_REFRESH_CMD_4—Self-Refresh Command Register 4
SELF_REFRESH_CMD_5—Self-Refresh Command Register 5
SELF_REFRESH_CMD_6—Self-Refresh Command Register 6
SELF_REFRESH_CMD_7—Self-Refresh Command Register 7
DQS_CONFIG_OFFSET_COUNT—DQS Config Offset Count
Register
DQS_CONFIG_OFFSET_TIME—DQS Config Offset Time
Register
DQS_DELAY_STATUS—DQS Delay Status Register
EXTRA_ATTRIB—DDR Extra Attributes Register
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 11-1. DRAM Controller memory map
Register
Chapter 2, “System Configuration and Memory
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
2
Reset Value
0x1000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Freescale Semiconductor
3
11.3.2.2.1/11-10
11.3.2.2.2/11-11
11.3.2.2.3/11-11
11.3.2.3/11-15
11.3.2.4/11-15
11.3.2.5/11-17
11.3.2.5/11-17
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11.3.2.5/11-17
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11.3.2.6/11-18
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Section/Page
11.3.2.1/11-5