MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 864

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32.2.4.15 Endpoint NAK Enable (USB_ENDPTNAKEN) Register
32-36
Address: Base + 0x17C
Reset
Reset
EPTNE
EPRNE
EPTN
EPRN
Field
Field
W
W
R
R
16
0
0
0
0
0
TX Endpoint NAK—Each TX endpoint has 1 bit in this field. The bit is set when the device sends a NAK
handshake on a received IN token for the corresponding endpoint.
EPTN[3]—Endpoint #3
EPTN[2]—Endpoint #2
EPTN[1]—Endpoint #1
EPTN[0]—Endpoint #0
RX Endpoint NAK—Each RX endpoint has 1 bit in this field. The bit is set when the device sends a NAK
handshake on a received OUT or PING token for the corresponding endpoint.
EPRN[3]—Endpoint #3
EPRN[2]—Endpoint #2
EPRN[1]—Endpoint #1
EPRN[0]—Endpoint #0
TX Endpoint NAK—Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and
the corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set.
EPTNE[3]—Endpoint #3
EPTNE[2]—Endpoint #2
EPTNE[1]—Endpoint #1
EPTNE[0]—Endpoint #0
RX Endpoint NAK—Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and
the corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set.
EPRNE[3]—Endpoint #3
EPRNE[2]—Endpoint #2
EPRNE[1]—Endpoint #1
EPRNE[0]—Endpoint #0
17
0
0
0
0
1
Figure 32-29. Endpoint NAK Enable (USB_ENDPTNAKEN) Register
18
0
0
0
0
2
Table 32-30. USB_ENDPTNAKEN field descriptions
19
Table 32-29. USB_ENDPTNAK field descriptions
0
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
20
4
0
0
0
0
21
0
0
0
0
5
22
0
0
0
0
6
23
0
0
0
0
7
Description
Description
24
8
0
0
0
0
25
9
0
0
0
0
10
26
0
0
0
0
11
27
0
0
0
0
12
28
0
0
Freescale Semiconductor
Access: User read/write
13
29
0
0
EPRNE
EPTNE
w1c
w1c
14
30
0
0
15
31
0
0