MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 965

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

If Test A is true and USB_FRINDEX[2:0] is zero or one, this is a case 2a or 2b scheduling boundary (see
Figure
condition.
If Test A and Test B evaluate to true, the host controller executes a complete-split transaction using the
transfer state of the current siTD. When the host controller commits to executing the complete-split
transaction, it updates QH[C-prog-mask] by bit-ORing with cMicroFrameBit. The transfer state is
advanced based on the completion status of the complete-split transaction. To advance the transfer state of
an IN siTD, the host controller must:
If the host controller encounters a condition where siTD [total bytes to transfer] is zero and it receives more
data, the host controller must not write the additional data to memory. The siTD [Status-Active] bit must
be cleared and the siTD [Status-Babble Detected] bit must be set. The fields siTD [Total Bytes To
Transfer], siTD [Current Offset], and siTD [P] are not required to be updated as a result of this transaction
attempt.
The host controller accepts (assuming good data packet CRC and sufficient room in the buffer as indicated
by the value of siTD [Total Bytes To Transfer]) MDATA and DATA0/1 data payloads as large as 192 bytes.
The host controller may optionally clear siTD [Status-Active] and set siTD [Status-Babble Detected] when
it receives MDATA or DATA0/1 with a data payload larger than 192 bytes. The following responses have
the noted effects:
Freescale Semiconductor
•
•
•
•
•
•
•
32-68). See
Decrement the number of bytes received from siTD [Total Bytes To Transfer]
Adjust siTD [Current Offset] by the number of bytes received
Adjust the siTD [P] (page select) field if the transfer caused the host controller to use the next page
pointer
Set any appropriate bits in the siTD [Status] field, depending on the results of the transaction.
ERR. The full-speed transaction completed with a time-out or bad CRC and this is a reflection of
that error to the host. The host controller sets the ERR bit in the siTD [Status] field and clears the
active bit.
Transaction Error (XactErr). The complete-split transaction encounters a timeout, CRC16 failure,
etc. The siTD [Status] field XactErr field is set and the complete-split transaction must be retried
immediately. The host controller must use an internal error counter to count the number of retries
as a counter field is not provided in the siTD data structure. The host controller does not retry more
than two times. If the host controller exhausts the retries or the end of the micro-frame occurs, the
active bit is cleared.
DATAx (0 or 1). This response signals the final data for the split transaction has arrived. The
transfer state of the siTD is advanced and the active bit is cleared. If the bytes to transfer field has
not decremented to zero (including the reception of the data payload in the DATAx response), less
End Algorithm
-- C-prog-mask to make sure it happened.
if previousBit bitAND siTD.C-mask then
End if
Return rvalue
Complete-Split for Scheduling Boundary Cases 2a, 2b
if not (previousBit bitAND siTD.C-prog-mask) then
End if
MPC5125 Microcontroller Reference Manual, Rev. 2
Universal Serial Bus Interface with On-The-Go
for details in managing this
rvalue = FALSE
32-137