MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 192

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Byte Data Link Controller (BDLC)
6-56
.
2. When an EOF is received, the IFR (and Message) is complete.
reception is complete
After BDLC module
The RxIFR interrupt is cleared when the received IFR byte is read from the BDLC Data Register.
After this is done, no further CPU intervention is necessary until the next IFR byte is received, and
this step is repeated. As with a message reception, all bytes of the IFR, including the CRC byte, are
placed into the BDLC Data Register as they are received for the CPU to retrieve.
After all IFR bytes (including the possible CRC byte) have been received from the bus, the bus is
idle again for a time period equal to an EOD symbol. Following this, the BDLC module determines
detects EOF, IFR
Figure 6-25. Receiving An IFR with the BDLC Module
B
Yes
MPC5125 Microcontroller Reference Manual, Rev. 2
DLCBSVR=0x1C/0x18?
DLCBSVR = 0x04?
DLCBSVR = 0x08?
Enter IFR Receive
(error detected)
receive routine
No
BDLC_
Exit IFR
Routine
(RxIFR)
BDLC_
BDLC_
(EOF)
No
No
A
Yes
Yes
in BDLC_DLCBDR
Discard received
(in case of LOA)
Store received
Is this an IFR
Read byte
reflection?
IFR bytes
IFR byte
Store received
transmit
IFR byte
Yes
B
No
Yes
B
BDLC_DLCBCR1[IMSG]
Freescale Semiconductor
of any interest?
Filter Received
Is this IFR
IFR Byte
Set
A
No