MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 393

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Fast Ethernet Controller (FEC)
14.5.1.2
Driver/DMA Operation with Receive BDs
Unlike transmit, the length of the receive frame is unknown by the driver ahead of time. Therefore, the
driver must set a variable to define the length of all receive buffers. In the FEC, this variable is written to
the ETH_R_BUFF_SIZE register.
The driver (receive BD software producer) should set up some number of empty buffers for the Ethernet
by initializing the address field and the E and W bits of the associated receive BDs. The hardware (receive
DMA) consumes these buffers by filling them with data as frames are received and clearing the E bit and
writing to the Lbit (1 indicates last buffer in frame), the frame status bits (if L= 1), and the length field.
If a receive frame spans multiple receive buffers, the L bit is only set for the last buffer in the frame. For
any other buffer, the length field in the receive BD is written with the default receive buffer length value
by the DMA (at the same time the e bit is cleared). For end-of-frame buffers, the receive BD is written with
L set and information written to the status bits (M, BC, MC, LG, NO, SH, CR, OV.TR). Some of the status
bits are error indicators that, if set, indicate the receive frame should be discarded and not given to higher
layers. The frame status/length information is written into the receive FIFO following the end of the frame
(as a single 32-bit word) by the receive logic. The length field for the end-of-frame buffer is written with
the length of the entire frame, not the length of the last buffer.
For simplicity, the driver may assign the default receive buffer length to be large enough to contain an
entire frame, keeping in mind that a malfunction on the network or out-of-specification implementation
could result in giant frames. Frames of 2 KB (2048 bytes) or larger are truncated by the FEC at 2047 bytes,
so software is guaranteed never to see a receive frame larger than 2047 bytes.
Similar to transmit, the FEC polls the receive descriptor ring after the driver sets up receive BDs and writes
to the ETH_R_DES_ACTIVE register. As frames are received, the FEC fills receive buffers and updates
the associated BDs, and then reads the next BD in the receive descriptor ring. If the FEC reads a receive
BD and finds the E bit equal to 0, it polls this BD once more. If the BD equals 0 a second time, the FEC
stops reading receive BDs until the driver writes to ETH_R_DES_ACTIVE.
14.5.2
Ethernet Receive Buffer Descriptor (RxBD)
In the RxBD, initialize the E and W bits in the first word and the pointer in the second word. When the
buffer has been filled by DMA, the Ethernet controller modifies the E, L, M, BC, MC, LG, NO, CR, OV,
and TR bits and also writes the data length into the first word. If a single receive buffer descriptor is used,
the data length is the portion of the data buffer used (the total length of the frame). If the received message
spans several data buffers, the data length in all but the last receive buffer (those with the L bit equaling 0)
is ETH_R_BUFF_SIZE. The data length of the last receive buffer descriptor (the descriptor where the L
bit is equal to 1) is the total length of the frame. The M, BC, MC, LG, NO, CR, OV, and TR bits in the first
word of the buffer descriptor are only modified by the Ethernet controller when the l bit is set.
MPC5125 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
14-37