MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 146

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Byte Data Link Controller (BDLC)
The TSIFR, TMIFR1, and TMIFR0 bits control the type of In-Frame Response being sent. The
programmer should not set more than one of these control bits to 1 at any given time. However, if more
than one of these three control bits are set to one, the priority encoding logic forces the internal register
bits to a known value as shown in the following table. However, when these bits are read, they are the same
as written earlier. For instance, if 011 is written to TSIFR, TMIFR1,and TMIFR0, then internally, they are
encoded as 010. However, when these bits are later read back, they are encoded as 011.
The BDLC supports the In-frame Response (IFR) feature of J1850 by setting these bits correctly. The four
types of J1850 IFR are shown in
or multiple nodes to acknowledge receipt of the data by responding to a received message after they have
seen the EOD symbol. For VPW modulation, the first bit of the IFR is always passive; therefore, an active
normalization bit must be generated by the responder and sent prior to its ID/address byte. When there are
multiple responders on the J1850 bus, only one normalization bit is sent, which assists all other
transmitting nodes to sync their responses.
The TSIFR bit is used to request the BDLC to transmit the byte in the BDLC Data Register as a single byte
IFR with no CRC. Typically, the byte transmitted is a unique identifier or address of the transmitting
(responding) node.
Set the TSIFR bit before the EOF following the main part of the message frame is received or no IFR
transmit attempts are made for the current message. If another node transmits an IFR to this message, set
the TSIFR bit before the normalization bit is received or no IFR transmit attempts are made for the
message. If another node does transmit a successful IFR or a reception error occurs, the TSIFR bit is
cleared. If not, the IFR is transmitted after the EOD of the next received message.
6-10
TMIFR1
TMIFR0
TSIFR
Field
Transmit Single Byte IFR with no CRC (Type 1 or 2)
0 The TSIFR bit is automatically cleared after the EOD if one or more IFR bytes has been received or an error
1 If this bit is set prior to a valid EOD being received with no CRC error and after the EOD symbol has been
Transmit Multiple Byte IFR with CRC (Type 3)
0 The TMIFR1 bit is automatically cleared once the BDLC module has successfully transmitted the CRC byte
1 If this bit is set prior to a valid EOD being received with no CRC error, once the EOD symbol has been
Transmit Multiple Byte IFR with no CRC (Type 3)
0 The TMIFR0 bit is automatically cleared once the BDLC module has successfully transmitted the EOD
1 If this bit is set prior to a valid EOD being received with no CRC error, once the EOD symbol has been
is detected on the bus.
received, the BDLC module attempts to transmit the appropriate normalization bit followed by the byte in
the BDLC Data Register.
and EOD symbol, by the detection of an error on the multiplex bus, a transmitter underrun, or loss of
arbitration.
received, the BDLC module attempts to transmit the appropriate normalization bit followed by IFR bytes.
The programmer should set TEOD after the last IFR byte has been written into BDLC Data Register. After
TEOD has been set and the last IFR byte has been transmitted, the CRC byte is transmitted.
symbol, by the detection of an error on the multiplex bus, a transmitter underrun, or loss of arbitration.
received the BDLC module attempts to transmit the appropriate normalization bit followed by IFR bytes.
The programmer should set TEOD after the last IFR byte has been written into BDLC Data Register. After
TEOD has been set, the last IFR byte to be transmitted is the last byte written into the BDLC Data Register.
Table 6-6. BDLC_DLCBCR2 field descriptions (continued)
MPC5125 Microcontroller Reference Manual, Rev. 2
Figure
6-5. The purpose of the in-frame response modes is to allow single
Description
Freescale Semiconductor