MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 159

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.4.2.3
The NB symbol has the same property as a logic 1 or a logic 0. It is only used in IFR message responses.
This bit is defined as an active bit.
6.4.2.4
The SOF symbol is defined as passive to active transition followed by an active period 200 µs in length
(see
regardless of whether it is a logic one or a logic zero.
6.4.2.5
The EOD symbol is defined as an active to passive transition followed by a passive period 200 µs in length
(see
6.4.2.6
The EOF symbol is defined as an active to passive transition followed by a passive period 280 µs in length
(see
80 µs the EOD becomes an EOF, indicating the completion of the message.
6.4.2.7
The IFS symbol is defined as a passive period 300 µs in length. The IFS symbol contains no transition,
since when used it always follows an EOF symbol.(see
6.4.2.8
The BREAK signal is defined as a passive to active transition followed by an active period of at least
240 µs (see
6.4.2.9
An IDLE is defined as a passive period greater than 3000 µs in length.
6.4.2.10
The timing tolerances for receiving data bits and symbols from the J1850 bus have been defined to allow
for variations in oscillator frequencies. In many cases the maximum time allowed to define a data bit or
symbol is equal to the minimum time allowed to define another data bit or symbol.
Because the minimum resolution of the BDLC module for determining which symbol is received equals a
single period of the MUX Interface clock (t
uncertainty of 1 t
Freescale Semiconductor
Figure 6-12
Figure 6-12
Figure 6-12
Figure 6-12
Normalization Bit (NB)
Start of Frame Symbol (SOF)
End of Data Symbol (EOD)
End of Frame Symbol (EOF)
Inter-Frame Separation Symbol (IFS)
Break Signal (BREAK)
IDLE
J1850 VPW Valid/Invalid Bits and Symbols
(e)). If there is no IFR byte transmitted after an EOD symbol is transmitted, after another
(c)). This allows the data bytes that follow the SOF symbol to begin with a passive bit,
(d)).
bdlc
due to sampling considerations.
(f)).
MPC5125 Microcontroller Reference Manual, Rev. 2
bdlc
), the receiver symbol timing boundaries are subject to an
Figure 6-12
(g))
Byte Data Link Controller (BDLC)
6-23