MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 796

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Secure Digital Host Controller (SDHC)
For a host read operation, the SDHC automatically transfers data into the next available buffer. If one of
the data buffers is full, the SDHC generates a DMA request. Conversely, for a host write operation, if one
of the data buffers is empty, the SDHC generates DMA requests. If some data is available, the SDHC reads
the data out of the buffer and writes it to the card through the SD bus interface.
28.4.1.1
The DMA/CPU accesses the SDHC data buffer as a FIFO through the 32-bit Data Buffer Access
(SDHC_BUFFER_ACCESS) register. Internally, the SDHC maintains a pointer into the data buffer.
Accesses to the SDHC_BUFFER_ACCESS register automatically increase the pointer value. The pointer
value is not directly accessible by the software. In cases when the block length of the data transfer is not a
multiple of 32 bits, the last access to the SDHC_BUFFER_ACCESS register contains valid data only on
8, 16, or 24 bits. Because the SDHC_BUFFER_ACCESS register only allows 32-bit accesses, put/fetch
the data bytes on the correct byte position of the SDHC_BUFFER_ACCESS register. For an 8-bit data
access to the FIFO, put/fetch data into SDHC_BUFFER_ACCESS bits 7 through 0. For 16-bit data access,
put/fetch data in SDHC_BUFFER_ACCESS bits 15 through 0. For a 24-bit data, put/fetch data into
SDHC_BUFFER_ACCESS bits 23 through 0.
When data is written to the card, a 32-bit data word in the data buffer is shifted out from the LSB byte to
the MSB byte. When data is read from the card, the data is shifted to the data buffer from LSB byte to MSB
byte. See
28-24
System IP Bus
Figure 28-17
SDHC Data Buffer
dma_req
sdhc_irq
Data Buffer Access
Figure 28-17. Data Swap Between System IP Bus and SDHC Data Buffer
IP Bus
for the data swap between system IP bus and SDHC data buffer.
I/F
31-24
MPC5125 Microcontroller Reference Manual, Rev. 2
Figure 28-16. SDHC Buffer Scheme
23-16
Buffer
SDHC Registers
X
Buffer Control
15-8
Buffer
Y
7-0
7-0
15-8
SD Bus
I/F
23-16
Freescale Semiconductor
31-24