MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 628

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MSCAN
22.4.11.1 Transmit Interrupt
At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message
for transmission. The TXEx flag of the empty message buffer is set.
22.4.11.2 Receive Interrupt
A message is successfully received and shifted into the foreground buffer (RxFG) of the receiver FIFO.
This interrupt is generated immediately after receiving the EOF symbol. The RXF flag is set. If there are
multiple messages in the receiver FIFO, the RXF flag is set as soon as the next message is shifted to the
foreground buffer.
22.4.11.3 Wake-Up Interrupt
Activity on the CAN bus occurred during MSCAN internal sleep mode and WUPE (see
“MSCAN Control 0 Register
22.4.11.4 Error Interrupt
An error interrupt is generated if an overrun of the receiver FIFO, error, warning, or bus-off condition
occurs. See
of the following conditions:
22.4.12 Interrupt Acknowledge
Interrupts are directly associated with one or more status flags in either the CANRFLG register (see
Section 22.3.2.5, “MSCAN Receiver Flag Register
Section 22.3.2.7, “MSCAN Transmitter Flag Register
one of the corresponding flags is set. The flags in these registers must be reset within the interrupt manager
to handshake the interrupt. The flags are reset by writing a 1 to the corresponding bit position.
22-50
•
•
Overrun – An overrun condition of the receiver FIFO as described in
Structures,”
CAN Status Change – The actual value of the transmit and receive error counters control the CAN
bus state of the MSCAN. As soon as the error counters skip into a critical range (Tx/Rx-warning,
Tx/Rx-error, bus-off) the MSCAN flags an error condition. The status change that caused the error
condition is indicated by the TSTAT and RSTAT flags (see
Flag Register (CANRFLG),”
(CANRIER)”).
Section 22.3.2.5, “MSCAN Receiver Flag Register (CANRFLG).”
Receive Interrupt (RXF)
Transmit Interrupts (TXE[2:0])
occurred.
Interrupt Source
(CANCTL0)”) enabled.
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 22-34. Interrupt Vectors (continued)
and
Section 22.3.2.6, “MSCAN Receiver Interrupt Enable Register
(CANRFLG)”) or the CANTFLG register (see
CCR Mask
(CANTFLG)”). Interrupts are pending as long as
I bit
I bit
CANRIER (RXFIE)
CANTIER (TXEIE[2:0])
Section 22.3.2.5, “MSCAN Receiver
Local Enable
Section 22.4.2.3, “Receive
An interrupt indicates one
Freescale Semiconductor
Section 22.3.2.1,