MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 798

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Secure Digital Host Controller (SDHC)
would be empty (the SDHC sets STATUS[YBUF_EMPTY] or STATUS[XBUF_EMPTY]) when these
buffer of data are fetched out of the buffer. The STATUS[BUF_READ_RDY] status bit and DMA request
would be set accordingly. From the software point of view, the buffer size becomes variable and equal to
the real data size that needs to be transferred. This eases the software programming of the SDHC, because
inserting dummy data to fill the buffer is not necessary.
28.4.1.5
Dividing Large Data Transfer
This SDIO command CMD53 definition limits the maximum size of data transfers according to this
formula.
Max Transfer Size = Block Size × Block Count
Eqn. 28-1
The block size can be a multiple of the size of the data buffer. However, it is recommended that the block
size be equal to the data buffer size. This allows the SDHC to stop the SD_CLK during block gaps should
an overflow or underrun condition occur. Stopping the SD_CLK while the data lines are active may cause
data corruption on some cards. If an application or card driver needs to transfer larger sets of data, the host
driver should divide the data set into multiple blocks.
The length of a multiple block transfer needs to be in block size units. If the total data length cannot be
divided evenly to a multiple of the block size, there are two ways to transfer the data depending on function
and card design. Option one is for the card driver to split the transaction into a block transfer to send most
of the data and a byte transfer to send the remaining data. Option two is to add filler data in the last block
to complete the block size. For option two, the card must manage to remove the filler data.
See
Figure 28-18
for an example showing dividing a large data set. The 544-byte WLAN frame is divided
into eight 64-byte blocks plus the block. Eight 64-byte blocks are sent in block transfer mode and the
remaining 32 bytes are sent in byte transfer mode.
MPC5125 Microcontroller Reference Manual, Rev. 2
28-26
Freescale Semiconductor