MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 320

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DRAM Controller
11-12
DRAM_TIME_WTR1
DRAM_TIME_RTW1
DRAM_TIME_RRD
DRAM_TIME_RCD
DRAM_TIME_CCD
DRAM_TIME_WR1
DRAM_TIME_RAS
DRAM_TIME_FAW
Timing Parameter
DRAM_TIME_RTP
DRAM_TIME_RPA
DRAM_TIME_RC
DRAM_TIME_RP
Controls JEDEC
(JEDEC spec)
Parameter
t
t
t
t
t
t
t
t
WTR
RRD
t
RCD
FAW
CCD
RAS
RTP
t
t
WR
—
RC
RP
RP
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 11-9. Timing Parameters (continued)
DRAM_TIME_RPA
WL + t
WL + t
t
WL + t
WL + t
DRAM_TIME_FAW
DRAM_TIME_RPA = t
RTP
DRAM_TIME_RRD = t
DRAM_TIME_RCD = t
CL - WL + 2 + t
CL - WL + 4 + t
DRAM_TIME_RAS = t
max(t
t
max(t
(All times in CSB clock
RTP
DRAM_TIME_RC = t
DRAM_TIME_RP = t
DRAM_TIME_WTR1 =
DRAM_TIME_RTW1 =
DRAM_TIME_CCD
DRAM_TIME_RTP
DRAM_TIME_WR1 =
+2 (16-bit mode, DDR2)
(32-bit mode, DDR2)
(8 bank device)
WTR
WTR
CCD
WR
WR
CCD
bank device)
Formulae
periods)
,2) (32-bit mode)
+ 2 (32-bit mode)
+ 4 (16-bit mode)
,4)(16-bit mode)
+ 2 (32-bit mode)
+ 4 (16-bit mode)
BTA
BTA
4
1
= t
(32-bit)
(16-bit)
= t
3
2
RP
RP
RC
RP
RRD
RAS
RCD
=
FAW
=
+ 1
(4
ACTIVE bank A to ACTIVE bank B command.
ACTIVE to ACTIVE (same bank) command.
ACTIVE to PRECHARGE command.
ACTIVE to READ or WRITE delay.
4-bank activate period.
CAS to CAS delay
Because time is needed for data to be sent over,
this time is minimum two clocks in 32-bit mode and
four clocks in 16-bit mode.
Read to precharge delay.
DRAM_TIME_RTP is the read-to-precharge delay
and t
hence, the difference for 16-bit mode.
Figure 11-7
Precharge command period.
Precharge all command period.
DRAM_TIME_WR1 is the write recovery time,
measured in clocks between write command and
precharge command. For this reason, WL (the
write latency) and the length of the actual write (2
or 4) need to be added to t
Figure 11-8
DRAM_TIME_WTR1 is the write to read time,
measured in clocks between write command and
read command. For this reason, WL (the write
latency) and the length of the actual write (2 or 4)
need to be added to t
Figure 11-9
DRAM_TIME_RTW1 is the read-to-write time,
measured in clocks between the read and write
command. There is no limitation on the DRAM on
how to set this parameter. The parameter should
be set such that there is no contention on the DQ
data bus when switching from read to write.
Equation given at left tries to come up with a
formulae that defines the minimum value of
DRAM_TIME_RTW1 to avoid contention. CL is the
cas latency, WL is the write latency, and t
bus turn-around time. t
time that needs to be put on the bus between the
MPC5125 driving the bus and the DRAM driving
the bus to take into account the transit delay on the
PCB, the pad delay, the DRAM skew, and the
on-chip delay.
RTP
is the internal read-to-precharge delay,
gives the details.
gives the details.
gives the details.
Description
WTR
BTA
.
Freescale Semiconductor
is the minimum dead
WR.
BTA
is the