MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 231

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.2.1
9.2.1.1
The 32-bit DMA control register (DMACR) defines the basic operating configuration of the DMA.
The DMA arbitrates channel service requests in groups of 16 channels. The 64 channel configurations
have four groups (3, 2, 1, and 0). Group 3 contains channels 63–48. Group 2 contains channels 47–32.
Group 1 contains channels 31–16. Group 0 contains channels 15–0.
Arbitration within a group can be configured to use a fixed priority or a round robin. In fixed priority
arbitration, the highest priority channel requesting service is selected to execute. The priorities are
assigned by the channel priority registers. In round robin arbitration mode, the channel priorities are
ignored and the channels within each group are cycled through without regard to priority.
The group priorities operate in a similar fashion. In group fixed priority arbitration mode, channel service
requests in the highest priority group are executed first where priority level 3 is the highest and priority
level 0 is the lowest. The group priorities are assigned in the GRPnPri registers. All group priorities must
have unique values before any channel service requests occur. Otherwise, a configuration error is reported.
Unused group priority registers, per configuration, are unimplemented in the DMACR. In group round
robin mode, the group priorities are ignored and the groups are cycled through without regard to priority.
Freescale Semiconductor
Address: Base + 0x0000
Reset
Reset
GRP3PRI
GRP2PRI
GRP1PRI
EDCG
Field
W
W
R
R
EDCG
GRP3PRI
16
0
1
0
Register Descriptions
DMA Control Register (DMACR)
Enable Clock Dynamic Gating
0 Disable clock dynamic gating.
1 Enable clock dynamic gating.
Channel Group 3 Priority. Group 3 priority level when fixed priority group arbitration is enabled.
Channel Group 2 Priority. Group 2 priority level when fixed priority group arbitration is enabled.
Channel Group 1 Priority. Group 1 priority level when fixed priority group arbitration is enabled.
17
0
0
1
1
GRP2PRI
18
0
0
1
2
19
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Figure 9-1. DMA Control Register (DMACR)
GRP1PRI
20
Table 9-4. DMACR field descriptions
4
0
0
0
21
0
0
1
5
GRP0PRI
22
0
0
0
6
23
0
0
0
7
Description
24
8
0
0
0
0
25
9
0
0
0
0
10
26
0
0
0
0
11
27
0
0
0
0
ERGA ERCA EDBG
Direct Memory Access (DMA)
12
28
0
0
0
Access: User read/write
13
29
0
0
0
14
30
0
0
0
15
31
9-11
0
0
0
0