MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 718

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Programmable Serial Controller (PSC)
25.5.2.2
The serial BCLK and the FrameSync can be inputs that come from an external codec device or they can
be internally generated by the PSC and provided as outputs to the external device, under control of the
SICR[GenClk] bit. When the SICR[GenClk] bit = 0, the BCLK and the FrameSync are inputs. In this case,
the FrameSync width can be anything from one BCLK period up to the total FrameSync length/period
minus one BCLK. If the GenClk bit = 1, the PSC generates the BCLK and the FrameSync signal.
Figure 25-46
The source for the internal clock generation is the
codec divided independently whether the PSC configured as a master (provides BCLK and FrameSync)
or as a slave (receives the clock signals).
Each PSC consists of a
as a master and the MCLK is available, the PSC generates both clock signals independently of whether the
25-40
Signal
Frame
MCLK
RxD
CLK
Codec Clock and FrameSync Generation
shows how the PSC generates the clocks.
Receiver Serial Data Input. Data received on RxD is sampled on the falling or rising edge of the clock signal.
Transfers can be specified as either LSB or MSB first.
Frame Sync. In codec mode Frame can be driven from an external Codec or can be generate by the internal
clock logic. Frame can be programmed as active High or active Low.
Bit Clock. In codec mode CLK is:
Clock output for an external codec
• Data sampled on the rising edge of CLK if SICR[ClkPol] equals 1
• Data sampled on the falling edge of CLK if SICR[ClkPol] equals 0
• Data sampled MSB first if SICR[SHDIR] equals 0
• Data sampled LSB first if SICR[SHDIR] equals 1
• The frame sync input from the external Codec if SICR[GenClk] equals 0
• The frame sync output to the external Codec if SICR[GenClk] equals 1
• Frame sync is active low if SICR[SyncPol] equals 0
• Frame sync is active high if SICR[SyncPol] equals 1
• The clock input from the external Codec if SICR[GenClk] equals 0
• The clock output to the external Codec if SICR[GenClk] equals 1
Table 25-30. PSC Signal Description for Codec Mode (continued)
CCR
MCLK
Figure 25-46. Clock Generation Diagram for Codec Mode
register to generate a BCLK and a FrameSync signal. If the PSC is configured
MPC5125 Microcontroller Reference Manual, Rev. 2
PSC
BCLK Divider
CCR[8:23]
MCLK.
Description
The PSC provides the clock to the external
Frame Divider
CTUR[0:7]
CCR[0:7]
Freescale Semiconductor
MCLK
Frame
BCLK