MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 905

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

32.5.7
This data structure is only for managing full- and low-speed transactions that span a host-frame boundary.
Software must not use an FSTN in the asynchronous schedule. An FSTN in the asynchronous schedule
results in undefined behavior. Software must not use the FSTN feature with a host controller whose
HCIVERSION register indicates a revision implementation below 0x0096. FSTNs were not defined for
EHCI implementations before revision 0.96 of the EHCI specification and their use may yield undefined
results.
32.5.7.1
The first doubleword of an FSTN contains a link pointer to the next schedule object. This object can be of
any valid periodic schedule data type.
Freescale Semiconductor
doubleword
31
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
5
6
6
6
6
8
9
9
Periodic Frame Span Traversal Node (FSTN)
Table 32-65. Host-Controller Rules for Bits in Overlay (doublewords 5, 6, 8 and 9)
QH Offset
FTSN Normal Path Pointer
0x14
0x18
0x18
0x18
0x18
0x20
0x24
0x24
C-prog-mas
FrameTag
NakCnt
S-bytes
Status
11:10
Figure 32-50. Frame Span Traversal Node Structure
Cerr
11:5
IOC
Bit
4:1
DT
7:0
4:0
31
15
0
k
MPC5125 Microcontroller Reference Manual, Rev. 2
Normal Path Link Pointer
Back Path Link Pointer
Nak counter—RW. This field is a counter the host controller decrements when a
transaction for the endpoint associated with this queue head results in a Nak or Nyet
response. This counter is reloaded from RL before a transaction is executed during
the first pass of the reclamation list (relative to an asynchronous list restart
condition). It is also loaded from RL during an overlay.
The data toggle control controls whether the host controller preserves this bit when
an overlay operation is performed.
Interrupt on complete. The IOC control bit is always inherited from the source qTD
when the overlay operation is performed.
Error counter. This two-bit field is copied from the qTD during the overlay and written
back during queue advancement.
Ping state (P)/ERR. If the EPS field indicates a high-speed endpoint, then this field
should be preserved during the overlay operation.
Split-transaction complete-split progress. This field is initialized to zero during any
overlay. This field is used to track the progress of an interrupt split-transaction.
Software must ensure that the S-bytes field in a qTD is zero before activating the
qTD. This field is used to keep track of the number of bytes sent or received during
an IN or OUT split transaction.
Split-transaction frame tag. This field is initialized to zero during any overlay. This
field is used to track the progress of an interrupt split-transaction.
15
14 13 12 11 10
Description
Universal Serial Bus Interface with On-The-Go
9
8
7
6
5
4
00
00
3
2
Typ
Typ
1
T 0x00
T 0x04
0
offset
32-77