MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 702

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Programmable Serial Controller (PSC)
25-24
Address: Base + 0x030
Reset
Reset
FrameSyncDiv
W
W
BCLKDiv
R
R
TimeOut
Field
16
0
0
0
0
17
0
0
0
1
Codec. Frame Sync Divider.
FrameSync is generated internally by dividing down the bit clock. The FrameSyncDiv defines the
number of bit clock cycles between two active frame edges:
For more information, see
Codec / SPI. Delay before SCK (DSCKL).
When the PSC is in SPI mode (SICR[SPI] = 1), the FrameSyncDiv divider is used to determine the
length of time the PSC delays after SS goes low/active before the first SCK transition of the serial
transfer. This is a feature that exists in a QSPI. The following equation determines the actual delay
before SCK:
Other Modes. Reserved.
The value 0x00 stops this counter and disables the clock generator.
Codec. Bit Clock Divider.
Bit clock is generated internally by dividing down the MCLK frequency as follows:
Codec SPI. Baud rate.
SCK is generated internally by dividing down the MCLK frequency as follows:
The minimum BCLKDiv for SPI mode is 3.
UART Modes. Time Out count value.
TimeOut[0:15] define the number of UART clock events before the Time_Out event occurred if
enabled.
Other Modes. Reserved.
18
0
0
0
2
DSCKL delay =
BCLK frequency =
Figure 25-29. Codec Clock Register for UART Modes (CCR)
FrameSync Length = FrameSyncDiv[0:7] + 1
SCK frequency =
TimeOut[8:15]
19
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
20
4
0
0
0
Table 25-19. CCR field descriptions
FrameSyncDiv[0:7] + 1)
MCLK Frequency
21
0
0
0
MCLK Frequency
BCLKDiv[0:15] + 1
MCLK Frequency
BCLKDiv[0:15] + 1
5
Section 25.5.2.3, “Transmitting and Receiving in Soft Modem Codec Mode.”
22
0
0
0
6
23
0
0
0
7
Description
24
8
0
0
0
25
9
0
0
0
10
26
0
0
0
TimeOut[0:7]
11
27
0
0
0
12
28
0
0
0
Freescale Semiconductor
Access: User read/write
13
29
0
0
0
14
30
0
0
0
15
31
0
0
0