MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 382

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Fast Ethernet Controller (FEC)
14.3.5.16 Descriptor Individual Address 1 (ETH_IADDR1) Register
The Descriptor Individual Address 1 (ETH_IADDR1) register contains the upper 32 bits of the 64-bit
individual address hash table used in the address recognition process to check for a possible match between
the DA field of receive frames and an individual DA. This register is not reset and must be initialized.
14-26
Address: Base + 0x0EC
Address: Base + 0x118
PAUSE_DUR
Reset
Reset
Reset
Reset
OPCODE
IADDR1
Field
Field
W
W
W
W
R
R
R
R
—
—
—
16
16
0
0
0
This is the opcode field used in pause frames. These bits have a constant value of 0x0001.
This is the pause duration field used in pause frames.
This field contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive
frames with a unicast address. Bit 31 of ETH_IADDR1 contains hash index bit 63. Bit 0 of ETH_IADDR1
contains hash index bit 32.
—
—
—
17
17
0
1
1
Figure 14-17. Descriptor Individual Address 1 (ETH_IADDR1) Register
Figure 14-16. Opcode/Pause Duration (ETH_OP_PAUSE) Register
—
—
—
18
18
0
2
2
19
—
—
19
—
0
3
3
Table 14-20. ETH_OP_PAUSE field descriptions
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 14-21. ETH_IADDR1 field descriptions
—
—
—
20
20
4
0
4
—
—
—
21
21
0
5
5
—
—
—
22
22
0
6
6
PAUSE_DUR
OPCODE
—
—
—
23
23
0
7
7
IADDR1
IADDR1
Description
Description
—
—
—
24
24
8
0
8
—
—
—
25
25
9
0
9
—
—
—
10
26
10
26
0
—
—
—
11
27
11
27
0
—
—
—
12
28
12
28
0
Freescale Semiconductor
Access: User read/write
Access: User read/write
—
—
—
13
29
13
29
0
—
—
—
14
30
14
30
0
—
—
—
15
31
15
31
1