MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 349

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

12.3.2.15 Summed Priority Counters
12.3.2.16 Counter Register Descriptions and Values
The counter registers contain 19 different 24-bit counter values. All these counter values count certain
events.
2, Summed Priority Counter 3 and Summed Priority Counter 4 are available in two sets of registers. They
are available in registers with the same name, but they are also available in a set of three other registers
(granted ack counter or cumulative wait counter registers). The multiple-mapping of the three upper
Summed Priority Counter registers allows easy and compact DMA transfer to memory. Because of the
multiple mapping, all 19 count values can be transferred to memory with a 64-byte DMA transfer starting
at address 0x100. The multiple mapping allows the DMA to get all information with a 64-byte transfer,
but some decompression is needed on decoding the data, while the CPU can read the 19 registers and mask
out the upper eight bits to get relevant information.
Freescale Semiconductor
Address: Base + 0x138 ( SUMMED_PRIORITY_CNTR0)
Reset
Reset
SUMMED PRIORITY
CUMULATIVE WAIT
COUNTERn[23:0]
COUNTERn[23:0]
W
W
R
R
Table 12-17
Base + 0x13C (SUMMED_PRIORITY_CNTR1)
Base + 0x140 (SUMMED_PRIORITY_CNTR2)
Base + 0x144 (SUMMED_PRIORITY_CNTR3)
Base + 0x148 (SUMMED_PRIORITY_CNTR4)
Field
16
Field
0
0
0
0
17
0
0
0
1
Table 12-16. SUMMED_PRIORITY_CNTRn Registers field descriptions
Table 12-15. CUMULATIVE_WAIT_CNTRn Registers field descriptions
gives the details on the nature of the event. Counter values Summed Priority Counter
18
0
0
0
2
Figure 12-16. Summed Priority Counter 0–4 Registers
19
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
20
4
0
0
0
SUMMED PRIORITY COUNTER 0 – 4[15:0]
21
0
0
0
5
22
0
0
0
6
23
0
0
0
7
24
8
0
0
Description
Description
SUMMED PRIORITY COUNTER 0 – 4[23:16]
25
9
0
0
Multi-port DRAM Controller Priority Manager
10
26
0
0
11
27
0
0
12
28
0
0
Access: User read-only
13
29
0
0
14
30
0
0
12-17
15
31
0
0