MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 155

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.4
The BDLC module allows the user to send and receive messages across an SAE J1850 serial
communication
basis, while the BDLC performs all of the network access, arbitration, message framing and error detection
duties.
6.4.1
As noted above and in
network. As such, all messages transmitted on the J1850 bus are structured using the format below. The
following sections describe this format and its meanings.
SAE J1850 states that each message has a maximum length of 101 bit times or 12 bytes (excluding SOF,
EOD, NB, and EOF).
6.4.1.1
All messages transmitted onto the J1850 bus must begin with an long active SOF symbol. This indicates
to any listeners on the J1850 bus the start of a new message transmission. The SOF symbol is not used in
the CRC calculation.
Freescale Semiconductor
TST_DIVTE_T4
TST_CRCV_T4 Status of the receive message CRC.
Idle
Field
IDLE
Functional Description
J1850 Frame Format
SOF
Start of Frame Symbol (SOF)
0 The module output Tx pin output normal signal.
1 The module output Tx pin output MUX interface clock (FBDLC).
0 Correct.
1 Incorrect.
This bit indicates when the BDLC module is idle.
0 BDLC module is either transmitting or receiving data.
1) BDLC module has received IFS and no data is being transmitted or received.
Note: BDLC module is only idle after receiving IFS. The IDLE bit is 0 during reset since the BDLC module
network.
.
(Data0)
Priority
needs to wait for an IFS before becoming idle. Noise on the bus will be filtered and the IDLE bit will
remain unchanged.
Section 6.1.1, “Features,”
User software manages each transmitted or received message on a byte-by-byte
Table 6-15. BDLC_DLCBSTAT field descriptions
Figure 6-11. J1850 Bus Message Format (VPW)
MPC5125 Microcontroller Reference Manual, Rev. 2
ID (Data1)
Message
the BDLC module communicates across an SAE J1850
DataN
Description
CRC
O
E
D
Optional
IFR
Byte Data Link Controller (BDLC)
EOF
F
S
I
Idle
6-19