MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 432

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

General Purpose I/O (GPIO)
16.3.1.3
The GPIO Data (GPIO_GPDAT) register shown in
pins.
16-4
Address: Base + 0x04
Address: Base + 0x08
Reset
Reset
Reset
Reset
D[0:31]
Field
W
W
W
W
R
R
R
R
D16
D16
D0
D0
16
16
0
0
0
0
0
0
GPIO Data (GPIO_GPDAT) Register
Bits D0–D31 of the GPIO_GPDAT register in GPIO1 are driven on the
GPIO 00–31 pins when configured as outputs, and reflect the state of the
GPIO 00–31 pins when configured as inputs.
Bits D0–D31 of the GPIO_GPDAT register in GPIO2 are driven on the
GPIO 32–63 pins when configured as outputs, and reflect the state of the
GPIO 32–63 pins when configured as inputs.
Output drive configuration. Indicates whether a pin is actively driven as an output or is an open-drain driver.
0 The I/O pin is actively driven as an output.
1 The I/O pin is an open-drain driver. As an output, the pin is driven active-low, otherwise it is tristated.
Note: For GPIO1, the D0–D3 bit have no meaning because the GPIO 00–03 pins are input only.
D17
D17
D1
D1
17
17
0
0
0
0
1
1
D18
D18
D2
D2
18
18
0
0
0
0
2
2
Figure 16-3. GPIO Open Drain Register (GPIO_GPODR)
D19
D19
D3
D3
19
19
0
0
0
0
Figure 16-4. GPIO Data Register (GPIO_GPDAT)
3
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 16-3. GPIO_GPODR field descriptions
D20
D20
D4
D4
20
20
4
0
0
4
0
0
D21
D21
D5
D5
21
21
0
0
0
0
5
5
D22
D22
D6
D6
22
22
0
0
0
0
6
6
NOTE
Figure 16-4
D23
D23
D7
D7
23
23
0
0
0
0
7
7
Description
D24
D24
D8
D8
24
24
8
0
0
8
0
0
carries the data in/out for individual GPIO
D25
D25
D9
D9
25
25
9
0
0
9
0
0
D10
D26
D10
D26
10
26
10
26
0
0
0
0
D11
D27
D11
D27
11
27
11
27
0
0
0
0
D12
D28
D12
D28
12
28
12
28
0
0
0
0
Freescale Semiconductor
Access: User read/write
Access: User read/write
D13
D29
D13
D29
13
29
13
29
0
0
0
0
D14
D30
D14
D30
14
30
14
30
0
0
0
0
D15
D31
D15
D31
15
31
15
31
0
0
0
0