MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 908

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
USB_USBCMD register. To communicate with devices via the periodic schedule, system software must
enable the periodic schedule by writing a one to the periodic schedule enable bit in the USB_USBCMD
register. The schedules can be turned on before the first port is reset (and enabled).
Any time the USB_USBCMD register is written, system software must ensure the appropriate bits are
preserved, depending on the intended operation.
32.6.1.1
The port power control (PPC) bit in the USB_HCSPARAMS register indicates whether the USB 2.0 host
controller has port power control. When the PPC bit is a one, the host controller supports port power
switches. Each available switch has an output enable. PPE is controlled based on the state of the
combination bits PPC bit, EHCI configured (CF) bit, and individual port power (PP) bits.
32.6.1.2
Host ports by definition are power providers on USB. Whether the ports are considered high- or
low-powered is a platform implementation issue. Each EHCI USB_PORTSCn register has an over-current
status and over-current change bit. The functionality of these bits is specified in the USB Specification
Revision 2.0.
32.6.2
The host controller provides an equivalent suspend and resume model as that defined for individual ports
in a USB 2.0 hub. Control mechanisms are provided to allow system software to suspend and resume
individual ports. The mechanisms allow the individual ports to be resumed completely via software
initiation. Other control mechanisms are provided to parameterize the host controller's response (or
sensitivity) to external resume events. In this discussion, host-initiated or software-initiated resumes are
called resume events/actions; bus-initiated resume events are called wake-up events. The classes of
wakeup events are:
Selective suspend is a feature supported by the USB_PORTSCn register. It places specific ports into a
suspend mode. This feature is a functional component for implementing the appropriate power
management policy implemented in a particular operating system. When system software intends to
suspend the bus, it should suspend the enabled port, then shut off the controller by setting the run/stop bit
in the USB_USBCMD register to a zero.
When a wake event occurs, the system resumes operation and system software must set the run/stop bit to
a one and resume the suspended port.
32-80
•
•
Remote-wakeup enabled device asserts resume signaling. Similar to USB 2.0 hubs, when in host
mode, the host controller responds to explicit device, resumes signaling, and wakes up the system
(if necessary).
Port connect and disconnect. Sensitivity to these events can be turned on or off by using the port
control bits in the USB_PORTSCn register. An over-current event does not wake the USB core.
Suspend/Resume
Port Power
Reporting Over-Current
MPC5125 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor