MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 483

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

18.3
The following sections describe the type of interrupts, interrupt configurations, and their priorities.
18.3.1
The IPIC is responsible for receiving hardware-generated interrupts from different sources (both internal
and external) along with prioritizing and delivering them to the CPU for servicing. The interrupt sources
are controlled by the IPIC unit and may cause three types of exceptions in the processor core. The int signal
is the main interrupt output from the IPIC to the processor core and causes the external interrupt
exception.The cint signal is the critical interrupt output from the IPIC to the processor core and causes the
critical external interrupt exception. The smi signal is the system management interrupt output from the
IPIC to the processor core and causes the system management interrupt exception. The machine check
exception is caused by the internal mcp signal generated by the IPIC, informing the processor of error
conditions, assertion of the external MCP request, and other conditions.
18.3.2
Figure 18-28
The interrupt controller allows masking of each interrupt source. When an unmasked interrupt source is
pending in the IPIC_SIPNRx register, the interrupt controller sends an interrupt request to the core. When
an interrupt is taken, the interrupt mask bit in the machine state register is cleared to disable further
interrupt requests to the Power Architecture core until software can manage them.
All interrupt sources are prioritized and bits are set in the system interrupt pending register (IPIC_SIPNRx,
IPIC_SEPNR) as interrupts occur regardless of whether they are masked in the IPIC. The prioritization of
the interrupt sources is flexible within the following groups:
Freescale Semiconductor
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•
MVEC
Field
The relative priority of the PSC4, PSC5, PSC6, PSC7, PSC8, PSC9, GPT8, and GPT9 internal
interrupt signals can be modified.
The relative priority of the FIFOCUSB2OTG1, and USB2OTG2 internal interrupt signals can be
modified.
Functional Description
Interrupt Types
Interrupt Configuration
shows the interrupt configuration of the MPC5125.
System management interrupt vector. Specifies a 7-bit unique number of the IPIC’s highest priority system
management interrupt source, pending to the core. When a system management interrupt request occurs,
IPIC_SMVCR can be read. If there are multiple system management interrupt sources, IPIC_SMVCR latches
the highest priority system management interrupt. The MVEC field correctly reflects all interrupt vectors (See
Table 18-4
The value of SMVEC cannot change while it is being read.
Note: While the upper 24 bits of this register are set to zero at the release of PORESET, they can and will
change during device operation. Therefore, when using the value of the MVEC field, be sure to mask
off the upper 24 bits of this register.
for details).
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 18-27. IPIC_SMVCR field descriptions
Description
Integrated Programmable Interrupt Controller (IPIC)
18-35