MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 179

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.4.6.2
Receiving a message using the BDLC module is extremely straight-forward. As each byte of a message is
received and placed into the BDLC Data Register, the BDLC module indicates this to the CPU with an Rx
Data Register Full (RDRF) status in the BDLC_DLCBSVR register. When an EOF symbol is received,
indicating to the CPU that the message is complete, this is reflected in the BDLC_DLCBSVR register.
Outlined below are the basic steps to be followed for receiving a message from the SAE J1850 bus with
the BDLC module. For an illustration of this sequence, refer to
6.4.6.3
No message filtering hardware is included on the BDLC module, so all message filtering functions must
be performed in software. Because the BDLC module handles each message on a byte-by-byte basis,
message filtering can be done as each byte is received, rather than after the entire message is complete.
This enables the CPU to decide while a message remains in progress whether or not that message is of any
interest.
At any point during a message, if the CPU determines that the message is of no interest the IMSG bit can
be set. Setting the IMSG bit commands the BDLC module not to update the BDLC_DLCBSVR register
until the next valid SOF is received. This prevents the CPU from having to service the BDLC module for
each byte of every message sent over the network.
Freescale Semiconductor
1. When an RDRF interrupt occurs, retrieve the data byte.
2. When an EOF is received, the message is complete.
When the first byte of a message following a valid SOF symbol is received that byte is placed in
the BDLC Data Register, and an RDRF state is reflected in BDLC_DLCBSVR. No indication of
the SOF reception is made, since the end of the previous message is marked by an EOF indication.
The first RDRF state following this EOF indication should allow the user to determine when a new
message begins.
The RDRF interrupt is cleared when the received byte is read from the BDLC Data Register. After
this is done, no further CPU intervention is necessary until the next byte is received, and this step
is repeated.
All bytes of the message, including the CRC byte, are placed into the BDLC Data Register as they
are received for the CPU to retrieve.
After all bytes (including the CRC byte) have been received from the bus, the bus is idle for a time
period equal to an EOD symbol. After the EOD symbol is received, the BDLC module verifies that
the CRC byte is correct. If the CRC byte is not correct, this is reflected in BDLC_DLCBSVR.
If no In-Frame Response bytes are transmitted following the EOD symbol, the EOD transitions
into an EOF symbol. When the EOF is received it is reflected in BDLC_DLCBSVR, indicating to
the user that the message is complete. If IFR bytes do follow the first EOD symbol, once they are
complete another EOD is transmitted, followed by an EOF.
After the EOF state is reflected in BDLC_DLCBSVR, this indicates to the user that the message is
complete, and that when another byte is received it is the first byte of a new message.
Receiving a Message with the BDLC Module
Filtering Received Messages
MPC5125 Microcontroller Reference Manual, Rev. 2
Figure
6-21.
Byte Data Link Controller (BDLC)
6-43