MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 154

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Byte Data Link Controller (BDLC)
6.3.2.8
The BDLC Status Register (BDLC_DLCBSTAT) indicates the status of the BLDC module.
Read: any time
Write: any time
6-18
Address: Base + 0x0D
BDLCE
BREAK
Reset
Field
W
R
BDLC Status Register (BDLC_DLCBSTAT)
BDLC Enable
This bit serves as a MUX interface clock (f
0
1 The MUX interface clock (f
Send BREAK signal
This bit determines whether the BDLC module generates a BREAK symbol.
0 The BDLC module does not generate a BREAK symbol.
1 The BDLC module immediately sends a Break signal on the bus, regardless of its current transmit or
After setting the BREAK bit it is automatically cleared after two IPB clock cycles.
The active Break signal causes any other transmitting module to stop transmitting immediately because it
loses arbitration. It is at least 280 µs long.
Note: When the BDLC is operating at the high bus speed all 4X symbol times are one fourth that shown,
0
0
0
place.
receive status.
continue running, allowing registers to be accessed.
The MUX interface clock (f
except for Break, which is transmitted the same length in 1X or 4X mode.
Figure 6-10. BDLC Status Register (BDLC_DLCBSTAT)
1
0
0
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 6-14. BDLC_DLCSCR field descriptions
0
0
2
bdlc
bdlc
) and BDLC module are enabled to allow J1850 communications to take
) is disabled, shutting down the BDLC module for power saving. Bus clocks
bdlc
0
0
3
) enable/disable for power savings.
Description
0
0
4
TST_DIVTE
_T4
0
5
TST_CRCV_
Freescale Semiconductor
Access: User read/write
T4
0
6
IDLE
0
7