MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 913

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H-Frame boundaries for the host controller correspond to increments of USB_FRINDEX[13:3].
Micro-frame numbers for the H-Frame are tracked by USB_FRINDEX[2:0]. B-Frame boundaries are
visible on the high-speed bus via changes in the SOF token's frame number. Micro-frame numbers on the
high-speed bus are only derived from the SOF token's frame number (the high-speed bus sees eight SOFs
with the same frame number value). H-Frames and B-Frames have the fixed relationship (B-Frames lag
H-Frames by one micro-frame time) illustrated in
naturally aligned to H-Frames. Software schedules transactions for full- and low-speed periodic endpoints
relative the H-Frames. The result is these transactions execute on the high-speed bus at exactly the right
time for the USB 2.0 hub periodic pipeline. As described in
(USB_FRINDEX) Register,”
called SOFV), which lags the USB_FRINDEX[13:3] bits by one micro-frame count.
illustrates the required relationship between the value of USB_FRINDEX and the value of SOFV. This lag
behavior can be accomplished by incrementing USB_FRINDEX[13:3] based on carry-out of the 7 to 0
increment of USB_FRINDEX[2:0] and incrementing SOFV based on the transition of 0 to 1 of
USB_FRINDEX[2:0].
Software can write to USB_FRINDEX.
Register,”
USB_FRINDEX.
Freescale Semiconductor
Micro-Frames
HC Periodic
Figure 32-54. Relationship of Periodic Schedule Frame Boundaries to Bus Frame Boundaries
Schedule
HS Bus
Frames
provides the requirements that software should adhere to when writing a new value in
7
0
SS
HC Periodic Schedule
Frame Boundaries
1
Full/Low-Speed
Interface Data Structure
Transaction
MPC5125 Microcontroller Reference Manual, Rev. 2
the SOF value can be implemented as a shadow register (in this example,
2
CS
H-Frame N
3
CS
B-Frame N
4
CS
Section 32.2.4.4, “USB Frame Index (USB_FRINDEX)
5
CS
6
Figure
7
0
32-54. The host controller's periodic schedule is
SS
Section 32.2.4.4, “USB Frame Index
1
Full/Low-Speed
Interface Data Structure
Transaction
HS/FS/LS Bus
Frame Boundaries
2
CS
H-Frame N+1
Universal Serial Bus Interface with On-The-Go
3
CS
B-Frame N+1
4
CS
5
CS
6
Table 32-70
7
0
1
2
32-85