MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 236

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Direct Memory Access (DMA)
The DMA error indicator and this error interrupt enable flag must be asserted before an error interrupt
request for a given channel is asserted. See
definition.
9.2.1.5
The DMA Set Enable Request (DMASERQ) register provides a simple memory-mapped mechanism to
set a given bit in the DMAERQH and DMAERQL registers to enable the DMA request for a given
channel. The data value on a register write causes the corresponding bit in the DMAERQH or DMAERQL
register to be set. A data value of 64 to 127 (regardless of the number of implemented channels) provides
a global set function, forcing the entire contents of the DMAERQH and DMAERQL registers to be
asserted. Reads of this register return all 0s. See
9-16
Address: Base + 0x0010
Address: Base + 0x0014
Reset
Reset
Reset
Reset
Field
EEIn
W
W
W
W
R EEI
R EEI
R EEI
R EEI
63
47
31
15
16
16
0
0
0
0
0
0
DMA Set Enable Request (DMASERQ)
Enable Error Interrupt n
0 The error signal for channel n does not generate an error interrupt.
1 The assertion of the error signal for channel n generates an error interrupt request.
EEI
EEI
EEI
EEI
62
46
30
14
17
17
0
0
0
0
1
1
Figure 9-5. DMA Enable Error Interrupt High (DMAEEIH) Register
Figure 9-6. DMA Enable Error Interrupt Low (DMAEEIL) Register
EEI
EEI
EEI
EEI
61
45
29
13
18
18
0
0
0
0
2
2
Table 9-7. DMAEEIH and DMAEEIL field descriptions
EEI
EEI
EEI
EEI
60
44
28
12
19
19
0
0
0
0
3
3
MPC5125 Microcontroller Reference Manual, Rev. 2
EEI
EEI
EEI
EEI
59
43
27
11
20
20
4
0
0
4
0
0
EEI
EEI
EEI
EEI
58
42
26
10
21
21
0
0
0
0
5
5
Figure 9-5
EEI
EEI
EEI
EEI
57
41
25
09
22
22
0
0
0
0
6
6
Figure 9-7
EEI
EEI
EEI
EEI
56
40
24
08
23
23
0
0
0
0
7
7
and
Description
EEI
EEI
EEI
EEI
55
39
23
07
Figure
24
24
8
0
0
8
0
0
and
Table 9-8
EEI
EEI
EEI
EEI
54
38
22
06
25
25
9
0
0
9
0
0
9-6, and
EEI
EEI
EEI
EEI
53
37
21
05
10
26
10
26
0
0
0
0
for the DMASERQ definition.
Table 9-7
EEI
EEI
EEI
EEI
52
36
20
04
11
27
11
27
0
0
0
0
EEI
EEI
EEI
EEI
51
35
19
03
12
28
12
28
0
0
0
0
Freescale Semiconductor
Access: User read/write
Access: User read/write
for the DMAEEI
EEI
EEI
EEI
EEI
50
34
18
02
13
29
13
29
0
0
0
0
EEI
EEI
EEI
EEI
49
33
17
01
14
30
14
30
0
0
0
0
EEI
EEI
EEI
EEI
48
32
16
00
15
31
15
31
0
0
0
0