MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 596

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MSCAN
22.3.2.7
The transmit buffer empty flags each have an associated interrupt enable bit in the CANTIER register.
Read: Anytime
Write: Anytime for TXEx flags when not in initialization mode; write of 1 clears flag, write of 0 ignored
22.3.2.8
This register contains the interrupt enable bits for the transmit buffer empty interrupt flags.
Read: Anytime
Write: Anytime when not in initialization mode
22-18
Address: Base + 0x0C
TXExIF
Reset
Field
W
R
MSCAN Transmitter Flag Register (CANTFLG)
MSCAN Transmitter Interrupt Enable Register (CANTIER)
The CANTFLG register is held in the reset state when the initialization
mode is active (INITRQ = 1 and INITAK = 1). This register is writable
again as soon as the initialization mode is left (INITRQ = 0 and
INITAK = 0).
Transmitter Buffer Empty. These flags indicate that the associated transmit message buffer is empty, and thus
not scheduled for transmission. The Power Architecture must clear the flag after a message is set up in the
transmit buffer and is due for transmission. The MSCAN sets the flag after the message is sent successfully.
The flag is also set by the MSCAN when the transmission request is successfully aborted due to a pending
abort request (see
masked, a transmit interrupt is pending while this flag is set.
Clearing a TXExIF flag also clears the corresponding ABTAKx (see
Message Abort Acknowledge
cleared (see
When listen-mode is active (see
cannot be cleared and no transmission is started.
Read and write accesses to the transmit buffer are blocked if the corresponding TXExIF bit is cleared
(TXExIF = 0) and the buffer is scheduled for transmission.
0 The associated message buffer is full (loaded with a message due for transmission).
1 The associated message buffer is empty (not scheduled).
0
0
0
Figure 22-9. MSCAN Transmitter Flag Register (CANTFLG)
Section 22.3.2.9, “MSCAN Transmitter Message Abort Request
1
0
0
MPC5125 Microcontroller Reference Manual, Rev. 2
Section 22.3.2.9, “MSCAN Transmitter Message Abort Request
Table 22-10. CANTFLG field descriptions
0
0
2
(CANTAAK)”). When a TXExIF flag is set, the corresponding ABTRQx bit is
Section 22.3.2.2, “MSCAN Control 1 Register
NOTE
0
0
3
Description
0
0
4
Section 22.3.2.10, “MSCAN Transmitter
TXE2IF
w1c
1
5
(CANTARQ)”).
(CANCTL1)”) the TXExIF flags
Freescale Semiconductor
(CANTARQ)”). If not
TXE1IF
Access: User read/write
w1c
1
6
TXE0IF
w1c
1
7