MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 495

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

19.1.2
The I
wires, serial data line (SDA) and serial clock line (SCL), carry information between this module and other
devices connected to the bus. A unique address recognizes each device. Also, each device can operate as
transmitter or receiver, depending on the function of the device. In addition to the transmitters and
receivers, devices can be masters or slaves. A master is the device that initiates a data transfer on the bus
and generates clock signals to permit that transfer. At that time, any device addressed is considered a slave.
See
Standard communication usually has four functional areas:
These activities are briefly described in the following sections.
19.1.3
A START signal is a high-to-low transition of SDA while SCL is high. This signal denotes the beginning
of a new data transfer and wakes up all slaves. Each data transfer may contain several data bytes.
When the bus is free (no master device is engaging the bus), SCL and SDA lines are at a logical high. A
master sends a START signal to initiate communications.
Freescale Semiconductor
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Table
Transmitter
Receiver
Master
Slave
2
C is a simple bidirectional two-wire bus for efficient device-to-device communication. The two
Arbitration loss with automatic mode switching from master to slave
Calling address identification interrupt
Start and stop signal generation/detection
Repeated start signal generation
Acknowledge bit generation/detection
Bus busy detection
Programmable glitch filter
START signal
Slave address transmission
Data transfer
STOP signal
19-1.
I
START Signal
2
C Controller
Term
MPC5125 Microcontroller Reference Manual, Rev. 2
Device that sends data to bus.
Device that receives data from bus.
Device that initiates transfer, generates SCL, and terminates transfer.
Device that is addressed by master.
Table 19-1. I
2
C Terminology
Description
Inter-Integrated Circuit (I
19-3
2
C)