MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 984

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32.8.3
The host uses a bus reset to initialize downstream devices. When a bus reset is detected, the USB controller
renegotiates its attachment speed, resets the device address to 0, and notifies the DCD by interrupt
(assuming the USB reset interrupt enable is set). After a reset is received, all endpoints (except endpoint
0) are disabled and the device controller cancels any primed transactions. The concept of priming is
clarified below, but the DCD must perform the following tasks when a reset is received:
Read the reset bit in the USB_PORTSCn register and make sure that remains active. A USB reset occurs
for a minimum of three ms and the DCD must reach this point in the reset cleanup before end of the reset
occurs; otherwise, a hardware reset of the device controller is recommended (rare.)
Writing a 1 to the USB controller reset bit in the USB_USBCMD reset can perform a hardware reset.
Free all allocated dTDs because they are no longer executed by the device controller. If this is the first time
the DCD is processing a USB reset event, it is likely that no dTDs have been allocated.
At this time, the DCD may release control back to the OS because no further changes to the device
controller are permitted until a port change detect is indicated.
After a port change detect, the device has reached the default state and the DCD can read the
USB_PORTSCn to determine if the device is operating in FS or HS mode. At this time, the device
controller has reached normal operating mode and DCD can begin enumeration.
In some applications, it may not be possible to enable one or more pipes while in FS mode. Beyond the
data rate issue, there is no difference in DCD operation between FS and HS modes.
32.8.3.1
32.8.3.1.1
To conserve power, the USB controller automatically enters the suspended state when no bus traffic has
been observed for a specified period. When suspended, the USB controller maintains any internal status,
including its address and configuration. In device mode, the attached devices must be prepared to suspend
32-156
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Clear all setup token semaphores by reading the USB_ENDPTSETUPSTAT register and writing
the same value back to the USB_ENDPTSETUPSTAT register.
Clear all the endpoint complete status bits by reading the USB_ENDPTCOMPLETE register and
writing the same value back to the USB_ENDPTCOMPLETE register.
Cancel all primed status by waiting until all bits in the USB_ENDPTPRIME are 0 and then writing
0xFFFF_FFFF to USB_ENDPTFLUSH.
Bus Reset
Suspend/Resume
A hardware reset causes the device to detach from the bus by clearing the
run/stop bit. Therefore, the DCD must completely re-initialize the USB
controller after a hardware reset.
The device DCD may use the FS/HS mode information to determine the
bandwidth mode of the device.
Suspend Description
MPC5125 Microcontroller Reference Manual, Rev. 2
NOTE
NOTE
Freescale Semiconductor