MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 431

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16.3.1
16.3.1.1
The GPIO Direction (GPIO_GPDIR) register shown in
GPIO pins.
16.3.1.2
The GPIO Open Drain Register (GPIO_GPODR) shown in
output drive structure.
Freescale Semiconductor
1
2
3
Address: Base + 0x00
Default absolute offset with IMMRBAR at default location of 0xFF40_0000. See
Memory Map (XLBMEN + Mem Map).”
In this column, R/W = Read/Write, R = Read-only, and W = Write-only.
In this column, the symbol “U” indicates one or more bits in a byte are undefined at reset. See the associated description for
more information.
Reset
Reset
D[0:31]
Field
W
W
R
R
D16
D0
16
0
0
0
Register Descriptions
GPIO Direction (GPIO_GPDIR) Register
GPIO Open Drain Register (GPIO_GPODR)
Bits D0–D31 of the GPIO_GPDIR register in GPIO1 set the I/O state of the
GPIO 00–31 pins. Bits D0–D31 of GPIO_GPDIR register in GPIO2 set the
Direction. Indicates whether a pin is used as an input or an output.
0 The corresponding pin is an input.
1 The corresponding pin is an output.
Note: For GPIO1, the D0–D3 bits have no meaning because the GPIO 00–03 pins are input only.
D17
D1
17
0
0
1
structure of the GPIO 00–31 pins. Bits D0–D31 of the GPIO_GPODR
Bits D0–D31 of the GPIO_GPODR register in GPIO1 set the driver
register in GPIO2 set the driver structure of the GPIO 32–63 pins.
D18
D2
18
0
0
2
Figure 16-2. GPIO Direction Register (GPIO_GPDIR)
D19
D3
19
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 16-2. GPIO_GPDIR field descriptions
D20
D4
20
4
0
0
I/O state of the GPIO 32–63pins.
D21
D5
21
0
0
5
D22
D6
22
0
0
6
NOTE
NOTE
D23
D7
23
0
0
7
Description
Figure 16-2
D24
D8
24
8
0
0
Figure 16-3
D25
D9
25
9
0
0
defines the direction of individual
Chapter 2, “System Configuration and
D10
D26
10
26
0
0
defines the individual GPIO pins
D11
D27
11
27
0
0
D12
D28
12
28
General Purpose I/O (GPIO)
0
0
Access: User read/write
D13
D29
13
29
0
0
D14
D30
14
30
0
0
D15
D31
15
31
16-3
0
0