MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 234

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Direct Memory Access (DMA)
9.2.1.3
The DMA Enable Request High (DMAERQH) and DMA Enable Request Low (DMAERQL) registers
provide a bit map for the implemented 64 channels to enable the request signal for each channel.
DMAERQH supports channels 63–32, while DMAEQRL covers channels 31–00. The state of any given
channel enable is directly affected by writes to this register; it is also affected by writes to the DMASERQ
and DMACERQ registers. The DMASERQ and DMACERQ registers are provided so that the request
enable for a single channel can easily be modified without the need to perform a read-modify-write
sequence to the DMAERQH or DMAERQL registers.
The DMA request input signal and this enable request flag must be asserted before a channel’s hardware
service request is accepted. The state of the DMA enable request flag does not affect a channel service
request made explicitly through software or a linked channel request.
As a given channel completes the processing of its major iteration count, a flag in the transfer control
descriptor (TCD) can affect the ending state of the DMAERQ bit for that channel. If the TCD.D_REQ bit
is set, the corresponding DMAERQ bit is cleared, disabling the DMA request. If the D_REQ bit is cleared,
the state of the DMAERQ bit is unaffected.
9-14
Field
DOE
DAE
NCE
SGE
DBE
SBE
DMA Enable Request (DMAERQH, DMAERQL)
Destination Address Error
0 No destination address configuration error.
1 The last recorded error was a configuration error detected in the TCD.DADDR field. TCD.DADDR is
Destination Offset Error
0 No destination offset configuration error.
1 The last recorded error was a configuration error detected in the TCD.DOFF field. TCD.DOFF is
NBYTES/CITER Configuration Error
0 No NBYTES/CITER configuration error.
1 The last recorded error was a configuration error detected in the TCD.NBYTES or TCD.CITER fields.
Scatter/Gather Configuration Error
0 No scatter/gather configuration error.
1 The last recorded error was a configuration error detected in the TCD.DLAST_SGA field. This field is
Source Bus Error
0 No source bus error.
1 The last recorded error was a bus error on a source read.
Destination Bus Error
0 No destination bus error.
1 The last recorded error was a bus error on a destination write.
inconsistent with TCD.DSIZE.
inconsistent with TCD.DSIZE.
TCD.NBYTES is not a multiple of TCD.SSIZE and TCD.DSIZE, or TCD.CITER is equal to zero, or
TCD.CITER.E_LINK is not equal to TCD.BITER.E_LINK.
checked at the beginning of a scatter/gather operation after major loop completion if TCD.E_SG is enabled.
TCD.DLAST_SGA is not on a 32-byte boundary.
Table 9-5. DMAES field descriptions (continued)
MPC5125 Microcontroller Reference Manual, Rev. 2
Description
Freescale Semiconductor