MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 92

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Reset
4.5.1
The Boot Mode Select (BMS) bit determines the default value of LPC CS0 and provides the reset vector
to the e300 core. The e300 MSR[IP] bit reflects the state which is latched by the BMS bit. The BMS bit
indicates to the e300 where in memory to fetch the first instruction.
4.5.2
The RTC module contains registers located on the V
level reset functions. These registers can only be reset by removing power from V
4.5.3
The JTAG state machine is reset by the assertion of the JTAG TRST pin. The JTAG circuitry is not affected
by the assertion of PORESET, HRESET or SRESET. Even if your system does not utilize a JTAG
connector, the JTAG TRST and TCLK pi
occur.
4.5.4
The e300 boot vector may be configured through use of the RST_CONF_ROM_LOC and
RST_CONF_BMS pins at reset (see
allow selection of the boot memory interface and/or e300 boot vector.
4.5.5
The e300 boot memory interface is selected by configuring the RST_CONF_ROM_LOC pin at reset. This
allows selection of either the local plus controller (LPC) or NAND flash controller as the boot memory
device. See
sequence for initializing the MPC5125. These initialization sequences are described in the following
sections.
4-6
BMS Operation
RTC at Reset
JTAG Reset
Boot Vector Selection
Boot Memory Interface Selection
Section 4.5.1, “BMS Operation,”
1
Valid only when ROM_LOC indicates NAND Flash Boot.
NFC Base Address
LPC CSBOOT Start
LPC CSBOOT End
e300 Boot Vector
Parameter
Parameter
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 4-4. BMS Impact On Memory Windows
Table 4-3. BMS Impact on Boot Vector
1
Section 4.5, “Reset Configuration Word
ns
BMS = 0 (boot low)
BMS = 0 (boot low)
must be tied to a defined state or undefined behavior may
for details. Each interface requires a unique boot strap
0x007F_FFFF
0x0000_0100
0x0000_0000
0x0000_0000
BAT
power domain that are not affected by system
BMS = 1 (boot high)
BMS = 1 (boot high)
0xFFFF_FFFF
0xFFF0_0100
0xFF80_0000
0xFFF0_0000
(RST_CONF)”). These pins
BAT
Freescale Semiconductor
.