MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 351

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The possibility to use unequal LUT SEL bitfields makes it possible to use the main look-up tables for
DRAM priority programming and the alternate look-up tables for performance monitoring. Making the
look-up tables independent increases the possibility of what can be monitored.
12.4
The priority manager calculates the outgoing priority for all five channels of multi-port DRAM controller.
The priority of any channel at a given time is a function of the request granting history of the DRAM
controller. A granted request is called an ACK, so this schema is called an ACK-based schema, because
the priority is determined by the history of which channels have been ACK-ed in the past and when.
The priority manager calculates the priorities in a dynamic way. This means, a priority is never constant,
but changes over time, even when the request is not serviced. As a request ages while its not being
serviced, its priority escalates to a higher level, and as the level increases, it is eventually serviced.
The DRAM controller has a built-in preference to offer repeat for any incoming read request. The repeat
goes on as long as the requesting channel keeps requesting, and its priority is greater than 0. When the
outgoing priority for any channel is 0, the DRAM controller no longer services or repeats the request. This
feature allows the priority manager to control the maximum repeat count for any incoming channel.
12.4.1
Priority calculation for all channels is independent. There is no direct cross-dependency of the priority of
one channel on the priority of another channel. The algorithm looks at the last N arbitration cycles on the
bus. N is a programmable number, set by the ACK_COUNTn bitfields in the PRIOMAN_CONFIG1
register, described in
won the bus, is summed up, and saturated to a maximum of 15. This number of 0 to 15 is input into the
applicable look-up table. LUT table 0 is for channel 0, LUT table 1 is for channel 1, and so on. The value
for the particular number is the priority code going to the multiport DRAM controller. If N is set to 16 and
the own channel was granted the bus four times in the last 16 bus grant, the index into the look-up table is
four. The PRIO4[3:0] bitfield of the relevant look-up table is the priority going to the multi-port DRAM
controller.
There are two look-up tables for every channel, the main and the alternate. The algorithm may switch
between both, depending on some settings. The default look-up table is the main. However, the alternate
is used if:
12.4.2
Figure 12-18
Freescale Semiconductor
•
•
The particular channel has been configured to look at the DIU incoming priority, and the DIU
incoming priority is eight or higher.
The particular channel has been configured to look at the congestion monitor, and this block
indicates the multi-port DRAM is congested.
Functional Description
Description of Operation — Overview
Block Diagram
contains a block diagram of the block.
Figure
12-2. For the last N arbitration cycles, the number of times the own channel
MPC5125 Microcontroller Reference Manual, Rev. 2
Multi-port DRAM Controller Priority Manager
12-19