MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 379

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

14.3.5.12 Transmit Control (ETH_X_CNTRL) Register
The Transmit Control (ETH_X_CNTRL) register is read/write and is written to configure the transmit
block. This register is cleared at system reset. Bits FDEN and HBC should be modified only when the
ETHER_EN bit of the ETH_ECNTRL register equals 0.
Freescale Semiconductor
Address: Base + 0x0C4
MULTCAST
Reset
Reset
FCE_DC
HASH
Field
W
W
R
R
16
0
0
0
0
0
The FCE_DC, MULTCAST, and HASH bits are not affected by PORESET
or HRESET.
This is a read-only view of the FCE bit in the ETH_R_CNTRL register.
This bit is set if the current receive frame contained a multicast destination address (the least significant bit of
the DA was set). It is cleared if the current receive frame does not correspond to a multicast address.
Corresponds to the hash value of the current receive frame’s destination address. The hash value is a 6-bit
field extracted from the least significant portion of the CRC register.
17
0
0
0
0
1
18
0
0
0
0
2
Figure 14-13. Transmit Control (ETH_X_CNTRL) Register
19
0
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 14-16. ETH_R_HASH field descriptions
20
4
0
0
0
0
21
0
0
0
0
5
22
0
0
0
0
6
NOTE
23
0
0
0
0
7
Description
24
8
0
0
0
0
25
9
0
0
0
0
10
26
0
0
0
0
PAUSE TFC_
RFC_
11
27
0
0
0
Fast Ethernet Controller (FEC)
PAUSE
12
28
0
0
0
Access: User read/write
FDEN HBC
13
29
0
0
0
14
30
0
0
0
GST
14-23
15
31
0
0
0