MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 553

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

21.2.1.1.9
1
2
21.2.1.2
There are seven 32-bit registers for the LPC (SCLPC).
The following registers are available:
Freescale Semiconductor
Address: Base + 0x038
The reset value is defined by the latched reset configuration word (RST_CONF). See
See bit description in
Reset
Reset
•
•
ALT[6:0]
TSIZE
Field
ALT7
Field
TSE
W
W
R
R
Section 21.2.1.2.1, “SCLPC Packet Size (LPC_SCLPC_PS) Register”
Section 21.2.1.2.3, “SCLPC Control (LPC_SCLPC_C) Register”
16
0
0
0
0
0
SCLPC Registers—0x0100
TSIZ and TS Enable (LPC_TTE) Register
Chip Select 7 address latch timing modification for multiplexed mode.
0 CS is asserted together with the assertion of Address latch (ALE).
1 CS is asserted (ALEN + 1) x LPC_CLK clocks after the deassertion of ALE.
Same as ALT7, but for CS6–CS0/Boot.
Transfer Start Enable bit. The reset value is RST_CONF_LPC_TS. See
Word (RST_CONF).”
0 Transfer Start Signal is driven high.
1 Transfer Start Signal is brought out.
Transfer Size Enable bit. The reset value is RST_CONF_LPC_TS. See
Word (RST_CONF).”
0 Transfer Size Signal is driven high.
1 Transfer Size Signal is brought out.
17
0
0
0
0
1
Table
18
0
0
0
0
2
21-11.
Figure 21-10. TSIZ and TS Enable (LPC_TTE) Register
19
0
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 21-10. LPC_ALTR field descriptions
Table 21-11. LPC_TTE field descriptions
20
4
0
0
0
0
21
0
0
0
0
5
22
0
0
0
0
6
23
0
0
0
0
7
Description
Description
24
8
0
0
0
0
25
9
0
0
0
0
10
26
0
0
0
0
Table
(0x0108)
Section 4.5, “Reset Configuration
Section 4.5, “Reset Configuration
11
27
0
0
0
0
4-2.
(0x0100)
LocalPlus Bus Controller (LPC)
12
28
0
0
0
0
Access: User read/write
13
29
0
0
0
0
—
TSE
14
30
0
0
1,2
SIZE
—
21-13
15
31
0
0
T
1,2